docs/specs/ppc-xive.rst

2 POWER9 XIVE interrupt controller
5 The POWER9 processor comes with a new interrupt controller
6 architecture, called XIVE as "eXternal Interrupt Virtualization
10 XIVE are to support a larger number of interrupt sources and to
22 - Interrupt Virtualization Source Engine (IVSE), or Source Controller
28 - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
29   Controller (VC). It handles event coalescing and perform interrupt
32 - Interrupt Virtualization Presentation Engine (IVPE) or Presentation
33   Controller (PC). It maintains the interrupt context state of each
34   thread and handles the delivery of the external interrupt to the
39                 XIVE Interrupt Controller
69     tctx: Thread interrupt Context registers
118 the processor HW threads. It maintains the interrupt context state of
121 XIVE thread interrupt context
133 Interrupt Management context. This context is a set of registers which
134 lets the thread handle priority management and interrupt
137 - Interrupt Priority Register  (PIPR)
138 - Interrupt Pending Buffer     (IPB)
145 The Thread Interrupt Management registers are accessible through a
146 specific MMIO region, called the Thread Interrupt Management Area
155 Interrupt flow from an O/S perspective
159 raises the bit corresponding to the priority of the pending interrupt
160 in the register IBP (Interrupt Pending Buffer) to indicate that an
162 Interrupt Priority Register (PIPR) is also updated using the IPB. This
168 CPU interrupt line is raised and the EO bit of the Notification Source
170 the O/S. The O/S acknowledges the interrupt with a special load in the
171 Thread Interrupt Management Area.
173 The O/S handles the interrupt and when done, performs an EOI using a
195 Finally, the XiveTCTX contains the interrupt state context of a thread,
198 when a notification is triggered. It also models the Thread Interrupt
200 the CPU for interrupt management.