include/usb/fotg210.h

25 	uint32_t otgisr;/* 0x84: OTG Interrupt Status Register */
26 	uint32_t otgier;/* 0x88: OTG Interrupt Enable Register */
28 	uint32_t isr;	/* 0xC0: Global Interrupt Status Register */
29 	uint32_t imr;	/* 0xC4: Global Interrupt Mask Register */
42 	uint32_t gimr;	/* 0x130: Group Interrupt Mask Register */
43 	uint32_t gimr0; /* 0x134: Group Interrupt Mask Register 0 */
44 	uint32_t gimr1; /* 0x138: Group Interrupt Mask Register 1 */
45 	uint32_t gimr2; /* 0x13c: Group Interrupt Mask Register 2 */
46 	uint32_t gisr;	/* 0x140: Group Interrupt Status Register */
47 	uint32_t gisr0; /* 0x144: Group Interrupt Status Register 0 */
48 	uint32_t gisr1; /* 0x148: Group Interrupt Status Register 1 */
49 	uint32_t gisr2; /* 0x14c: Group Interrupt Status Register 2 */
105 /* OTG Interrupt Status Register */
116 /* OTG Interrupt Enable Register */
127 /* Global Interrupt Status Register (W1C) */
128 #define ISR_HOST            (1 << 2)  /* USB Host interrupt */
129 #define ISR_OTG             (1 << 1)  /* USB OTG interrupt */
130 #define ISR_DEV             (1 << 0)  /* USB Device interrupt */
133 /* Global Interrupt Mask Register */
134 #define IMR_IRQLH           (1 << 3)  /* Interrupt triggered at level-high */
135 #define IMR_IRQLL           (0 << 3)  /* Interrupt triggered at level-low */
136 #define IMR_HOST            (1 << 2)  /* USB Host interrupt */
137 #define IMR_OTG             (1 << 1)  /* USB OTG interrupt */
138 #define IMR_DEV             (1 << 0)  /* USB Device interrupt */
148 #define DEVCTRL_GIRQ_EN     (1 << 2)  /* Global Interrupt Enabled */
198 /* Group Interrupt Mask(Disable) Register */
199 #define GIMR_GRP2           (1 << 2) /* Disable interrupt group 2 */
200 #define GIMR_GRP1           (1 << 1) /* Disable interrupt group 1 */
201 #define GIMR_GRP0           (1 << 0) /* Disable interrupt group 0 */
204 /* Group Interrupt Mask(Disable) Register 0 (CX) */
205 #define GIMR0_CXABORT       (1 << 5) /* CX command abort interrupt */
206 #define GIMR0_CXERR         (1 << 4) /* CX command error interrupt */
207 #define GIMR0_CXEND         (1 << 3) /* CX command end interrupt */
208 #define GIMR0_CXOUT         (1 << 2) /* EP0-OUT packet interrupt */
209 #define GIMR0_CXIN          (1 << 1) /* EP0-IN packet interrupt */
210 #define GIMR0_CXSETUP       (1 << 0) /* EP0-SETUP packet interrupt */
213 /* Group Interrupt Mask(Disable) Register 1 (FIFO) */
221 /* Group Interrupt Mask(Disable) Register 2 (Device) */
226 #define GIMR2_ZLPRX         (1 << 6)  /* Zero-Length-Packet Rx Interrupt */
227 #define GIMR2_ZLPTX         (1 << 5)  /* Zero-Length-Packet Tx Interrupt */
228 #define GIMR2_ISOCABT       (1 << 4)  /* ISOC Abort Interrupt */
229 #define GIMR2_ISOCERR       (1 << 3)  /* ISOC Error Interrupt */
230 #define GIMR2_RESUME        (1 << 2)  /* Resume state change Interrupt */
231 #define GIMR2_SUSPEND       (1 << 1)  /* Suspend state change Interrupt */
232 #define GIMR2_RESET         (1 << 0)  /* Reset Interrupt */
235 /* Group Interrupt Status Register */
236 #define GISR_GRP2           (1 << 2) /* Interrupt group 2 */
237 #define GISR_GRP1           (1 << 1) /* Interrupt group 1 */
238 #define GISR_GRP0           (1 << 0) /* Interrupt group 0 */
240 /* Group Interrupt Status Register 0 (CX) */
241 #define GISR0_CXABORT       (1 << 5) /* CX command abort interrupt */
242 #define GISR0_CXERR         (1 << 4) /* CX command error interrupt */
243 #define GISR0_CXEND         (1 << 3) /* CX command end interrupt */
244 #define GISR0_CXOUT         (1 << 2) /* EP0-OUT packet interrupt */
245 #define GISR0_CXIN          (1 << 1) /* EP0-IN packet interrupt */
246 #define GISR0_CXSETUP       (1 << 0) /* EP0-SETUP packet interrupt */
248 /* Group Interrupt Status Register 1 (FIFO) */
254 /* Group Interrupt Status Register 2 (Device) */
259 #define GISR2_ZLPRX         (1 << 6)  /* Zero-Length-Packet Rx Interrupt */
260 #define GISR2_ZLPTX         (1 << 5)  /* Zero-Length-Packet Tx Interrupt */
261 #define GISR2_ISOCABT       (1 << 4)  /* ISOC Abort Interrupt */
262 #define GISR2_ISOCERR       (1 << 3)  /* ISOC Error Interrupt */
263 #define GISR2_RESUME        (1 << 2)  /* Resume state change Interrupt */
264 #define GISR2_SUSPEND       (1 << 1)  /* Suspend state change Interrupt */
265 #define GISR2_RESET         (1 << 0)  /* Reset Interrupt */
268 #define RXZLP_EP(x)         (1 << ((x) - 1)) /* EPx ZLP rx interrupt */
271 #define TXZLP_EP(x)         (1 << ((x) - 1)) /* EPx ZLP tx interrupt */