| /openbmc/linux/drivers/fpga/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
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| H A D | ts73xx-fpga.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Technologic Systems TS-73xx SBC FPGA loader
7 * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
8 * TS-7300, heavily based on load_fpga.c in their vendor tree.
17 #include <linux/fpga/fpga-mgr.h>
39 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write_init()
41 /* Reset the FPGA */ in ts73xx_fpga_write_init()
42 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
44 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
53 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write()
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| /openbmc/linux/drivers/net/can/ctucanfd/ |
| H A D | Kconfig | 2 tristate "CTU CAN-FD IP core" if COMPILE_TEST
4 This driver adds support for the CTU CAN FD open-source IP core.
8 is available (https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top).
9 Implementation on Intel FPGA-based PCI Express board is available
10 from project (https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd) and
11 on Intel SoC from project (https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd).
15 tristate "CTU CAN-FD IP core PCI/PCIe driver"
19 This driver adds PCI/PCIe support for CTU CAN-FD IP core.
20 The project providing FPGA design for Intel EP4CGX15 based DB4CGX15
22 at https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd .
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| /openbmc/linux/drivers/watchdog/ |
| H A D | pika_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * PIKA FPGA based Watchdog Timer
29 #define DRV_NAME "PIKA-WDT"
50 void __iomem *fpga; member
71 /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- in pikawdt_reset()
76 * Bit 8-11, WTCHDG_TIMEOUT_SEC: Sets the watchdog timeout value in in pikawdt_reset()
80 unsigned reset = in_be32(pikawdt_private.fpga + 0x14); in pikawdt_reset()
81 /* enable with max timeout - 15 seconds */ in pikawdt_reset()
83 out_be32(pikawdt_private.fpga + 0x14, reset); in pikawdt_reset()
118 return -EBUSY; in pikawdt_open()
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| /openbmc/u-boot/cmd/ |
| H A D | fpgad.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * based on cmd_mem.c
22 * FPGA Memory Display
25 * fpgad {fpga} {addr} {len}
31 unsigned int fpga; in do_fpga_md() local
41 fpga = dp_last_fpga; in do_fpga_md()
50 * FPGA is specified since argc > 2 in do_fpga_md()
52 fpga = simple_strtoul(argv[1], NULL, 16); in do_fpga_md()
73 fpga_get_reg(fpga, in do_fpga_md()
74 (u16 *)fpga_ptr[fpga] + addr in do_fpga_md()
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| /openbmc/linux/Documentation/driver-api/ |
| H A D | men-chameleon-bus.rst | 31 ----------------------
35 based devices.
38 -----------------------------------------
40 The current implementation is limited to PCI and PCIe based carrier devices
44 - Multi-resource MCB devices like the VME Controller or M-Module carrier.
45 - MCB devices that need another MCB device, like SRAM for a DMA Controller's
47 - A per-carrier IRQ domain for carrier devices that have one (or more) IRQs
48 per MCB device like PCIe based carriers with MSI or MSI-X support.
55 - The MEN Chameleon Bus itself,
56 - drivers for MCB Carrier Devices and
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| H A D | xillybus.rst | 2 Xillybus driver for generic FPGA interface
10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
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| /openbmc/u-boot/Documentation/devicetree/bindings/misc/ |
| H A D | gdsys,io-endpoint.txt | 1 gdsys IO endpoint of IHS FPGA devices
3 The IO endpoint of IHS FPGA devices is a packet-based transmission interface
5 FPGA's main ethernet connection.
8 - compatible: must be "gdsys,io-endpoint"
9 - reg: describes the address and length of the endpoint's register map (within
10 the FPGA's register space)
15 compatible = "gdsys,io-endpoint";
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| /openbmc/linux/drivers/mcb/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 FPGA based devices. It is used to identify MCB based IP-Cores within
14 an FPGA and provide the necessary framework for instantiating drivers
21 tristate "PCI based MCB carrier"
26 This is a MCB carrier on a PCI device. Both PCI attached on-board
30 If build as a module, the module is called mcb-pci.ko
33 tristate "LPC (non PCI) based MCB carrier"
39 If build as a module, the module is called mcb-lpc.ko
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| /openbmc/linux/arch/powerpc/boot/ |
| H A D | ebony.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on earlier code:
9 * Copyright 2002-2005 MontaVista Software Inc.
30 #define EBONY_FPGA_PATH "/plb/opb/ebc/fpga"
32 #define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash"
38 u8 *fpga; in ebony_flashsel_fixup() local
43 fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH); in ebony_flashsel_fixup()
45 if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga)) in ebony_flashsel_fixup()
46 fatal("%s has missing or invalid virtual-reg property\n\r", in ebony_flashsel_fixup()
49 fpga_reg0 = in_8(fpga); in ebony_flashsel_fixup()
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| /openbmc/linux/include/uapi/linux/ |
| H A D | fpga-dfl.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Header File for FPGA DFL User API
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 * The IOCTL interface for DFL based FPGA is designed for extensibility by
38 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
47 * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
58 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
60 * Reset the FPGA Port and its AFU. No parameters are supported.
64 * Return: 0 on success, -errno of failure
70 * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
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| /openbmc/linux/Documentation/fpga/ |
| H A D | dfl.rst | 2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
10 - Xu Yilun <yilun.xu@intel.com>
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
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| /openbmc/u-boot/board/armadeus/apf27/ |
| H A D | fpga.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2002-2013
6 * based on the files by
13 #include <asm/arch/imx-regs.h>
18 #include "fpga.h"
44 xilinx_desc fpga[CONFIG_FPGA_COUNT] = { variable
83 * Set the FPGA's active-low program line to the specified level
87 debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__, in fpga_pgm_fn()
94 * Set the FPGA's active-high clock line to the specified level
98 debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__, in fpga_clk_fn()
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| /openbmc/u-boot/board/imgtec/xilfpga/ |
| H A D | README | 10 MIPSfpga is an FPGA based development platform by Imagination Technologies
11 As we are dealing with a MIPS core instantiated on an FPGA, specifications
15 Digilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about
18 - microAptiv UP core m14Kc
19 - 50MHz clock speed
20 - 128Mbyte DDR RAM at 0x0000_0000
21 - 8Kbyte RAM at 0x1000_0000
22 - axi_intc at 0x1020_0000
23 - axi_uart16550 at 0x1040_0000
24 - axi_gpio at 0x1060_0000
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| /openbmc/linux/arch/powerpc/boot/dts/fsl/ |
| H A D | gef_ppc9a.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
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| H A D | gef_sbc310.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00010000>; // FPGA
39 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
41 bank-width = <2>;
42 device-width = <2>;
43 #address-cells = <1>;
44 #size-cells = <1>;
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| H A D | gef_sbc610.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,sbc610-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
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| H A D | ge_imp3a.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
7 * Based on: P2020 DS Device Tree Source
11 /include/ "p2020si-pre.dtsi"
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
39 bank-width = <2>;
40 device-width = <1>;
45 read-only;
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| /openbmc/qemu/docs/system/arm/ |
| H A D | mps2.rst | 1 …ards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521…
4 These board models use Arm M-profile or R-profile CPUs.
6 The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a
7 bigger FPGA but is otherwise the same as the 2; the 3 has a bigger
8 FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash).
10 Since the CPU itself and most of the devices are in the FPGA, the
12 FPGA image.
14 QEMU models the following FPGA images:
16 FPGA images using M-profile CPUs:
18 ``mps2-an385``
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| /openbmc/linux/drivers/media/pci/cx23885/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
48 This is a video4linux driver for Conexant 23885 based
55 tristate "Altera FPGA based CI module"
59 An Altera FPGA CI module for NetUP Dual DVB-T/C RF CI card.
62 module will be called altera-ci
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| /openbmc/u-boot/arch/arm/mach-aspeed/ast2600/ |
| H A D | Kconfig | 12 bool "EVB-AST2600"
15 EVB-AST2600 is Aspeed evaluation board for AST2600A0 chip.
21 bool "FPGA-AST2600"
24 FPGA-AST2600 is Aspeed FPGA board for AST2600 chip.
26 most implementation is co-code with EVB-AST2600.
29 bool "SLT-AST2600"
32 SLT-AST2600 is Aspeed SLT board for AST2600 chip.
35 bool "AST2600-IBM"
38 AST2600-IBM is IBM boards for AST2600 BMC based P0WER10+ servers
41 bool "AST2600-INTEL"
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| /openbmc/u-boot/arch/arm/mach-socfpga/ |
| H A D | reset_manager_gen5.c | 1 // SPDX-License-Identifier: GPL-2.0+
18 /* Assert or de-assert SoCFPGA reset manager reset. */
26 reg = &reset_manager_base->mpu_mod_reset; in socfpga_per_reset()
29 reg = &reset_manager_base->per_mod_reset; in socfpga_per_reset()
32 reg = &reset_manager_base->per2_mod_reset; in socfpga_per_reset()
35 reg = &reset_manager_base->brg_mod_reset; in socfpga_per_reset()
38 reg = &reset_manager_base->misc_mod_reset; in socfpga_per_reset()
60 writel(~l4wd0, &reset_manager_base->per_mod_reset); in socfpga_per_reset_all()
61 writel(0xffffffff, &reset_manager_base->per2_mod_reset); in socfpga_per_reset_all()
65 * Release peripherals from reset based on handoff
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| /openbmc/u-boot/drivers/pci/ |
| H A D | Kconfig | 16 orgnising devices in U-Boot. For PCI, driver model keeps track of
36 Armada37x0 SoCs. The PCIe controller on Armada37x0 is based on
55 bool "Generic ECAM-based PCI host controller support"
59 Say Y here if you want to enable support for generic ECAM-based
63 bool "Enable Armada-8K PCIe driver (DesignWare core)"
68 Armada-8K SoCs. The PCIe controller on Armada-8K is based on
99 support to work (e.g. beaver, jetson-tk1).
117 bool "Intel FPGA PCIe support"
121 FPGA, example Stratix 10.
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| /openbmc/linux/arch/powerpc/platforms/86xx/ |
| H A D | gef_sbc310.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
12 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
26 #include <asm/pci-bridge.h>
56 * There is a simple interrupt handler in the main FPGA, this needs in gef_sbc310_init_irq()
59 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic"); in gef_sbc310_init_irq()
61 printk(KERN_WARNING "SBC310: No FPGA PIC\n"); in gef_sbc310_init_irq()
81 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs"); in gef_sbc310_setup_arch()
121 /* Return the FPGA revision */
138 ('A' + gef_sbc310_get_board_rev() - 1)); in gef_sbc310_show_cpuinfo()
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| H A D | gef_sbc610.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
12 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
26 #include <asm/pci-bridge.h>
56 * There is a simple interrupt handler in the main FPGA, this needs in gef_sbc610_init_irq()
59 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic"); in gef_sbc610_init_irq()
61 printk(KERN_WARNING "SBC610: No FPGA PIC\n"); in gef_sbc610_init_irq()
82 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs"); in gef_sbc610_setup_arch()
113 /* Return the FPGA revision */
129 ('A' + gef_sbc610_get_board_rev() - 1)); in gef_sbc610_show_cpuinfo()
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