armadeus/apf27/fpga.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * (C) Copyright 2002-2013
6  * based on the files by
13 #include <asm/arch/imx-regs.h>
18 #include "fpga.h"
44 xilinx_desc fpga[CONFIG_FPGA_COUNT] = {  variable
83  * Set the FPGA's active-low program line to the specified level
87 	debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,  in fpga_pgm_fn()
94  * Set the FPGA's active-high clock line to the specified level
98 	debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,  in fpga_clk_fn()
105  * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
122  * Test the state of the active-high FPGA DONE pin
132  * Set the FPGA's wr line to the specified level
136 	debug("%s:%d: FPGA RW... %s ", __func__, __LINE__,  in fpga_wr_fn()
144 	debug("%s:%d: FPGA CS %s ", __func__, __LINE__,  in fpga_cs_fn()
152 	debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__,  in fpga_rdata_fn()
161 	debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__,  in fpga_wdata_fn()
180 	debug("%s:%d: FPGA POST ", __func__, __LINE__);  in fpga_post_fn()
197 	/* Configure FPGA CLKO */  in apf27_fpga_setup()
198 	writel(ACFG_CCSR_VAL, &pll->ccsr);  in apf27_fpga_setup()
200 	/* Configure strentgh for FPGA */  in apf27_fpga_setup()
201 	writel(ACFG_DSCR10_VAL, &system->dscr10);  in apf27_fpga_setup()
202 	writel(ACFG_DSCR3_VAL, &system->dscr3);  in apf27_fpga_setup()
203 	writel(ACFG_DSCR7_VAL, &system->dscr7);  in apf27_fpga_setup()
204 	writel(ACFG_DSCR2_VAL, &system->dscr2);  in apf27_fpga_setup()
208  * Initialize the fpga.  Return 1 on success, 0 on failure.
219 		debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);  in APF27_init_fpga()
220 		fpga_add(fpga_xilinx, &fpga[i]);  in APF27_init_fpga()