1*ebf2b9e3SZubair Lutfullah Kakakhel/* 2*ebf2b9e3SZubair Lutfullah Kakakhel * Copyright (C) 2016, Imagination Technologies Ltd. 3*ebf2b9e3SZubair Lutfullah Kakakhel * 4*ebf2b9e3SZubair Lutfullah Kakakhel * Zubair Lutfullah Kakakhel, Zubair.Kakakhel@imgtec.com 5*ebf2b9e3SZubair Lutfullah Kakakhel */ 6*ebf2b9e3SZubair Lutfullah Kakakhel 7*ebf2b9e3SZubair Lutfullah KakakhelMIPSfpga 8*ebf2b9e3SZubair Lutfullah Kakakhel======================================= 9*ebf2b9e3SZubair Lutfullah Kakakhel 10*ebf2b9e3SZubair Lutfullah KakakhelMIPSfpga is an FPGA based development platform by Imagination Technologies 11*ebf2b9e3SZubair Lutfullah KakakhelAs we are dealing with a MIPS core instantiated on an FPGA, specifications 12*ebf2b9e3SZubair Lutfullah Kakakhelare fluid and can be varied in RTL. 13*ebf2b9e3SZubair Lutfullah Kakakhel 14*ebf2b9e3SZubair Lutfullah KakakhelThe example project provided by IMGTEC runs on the Nexys4DDR board by 15*ebf2b9e3SZubair Lutfullah KakakhelDigilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about 16*ebf2b9e3SZubair Lutfullah Kakakhelthe example project and the Nexys4DDR board: 17*ebf2b9e3SZubair Lutfullah Kakakhel 18*ebf2b9e3SZubair Lutfullah Kakakhel- microAptiv UP core m14Kc 19*ebf2b9e3SZubair Lutfullah Kakakhel- 50MHz clock speed 20*ebf2b9e3SZubair Lutfullah Kakakhel- 128Mbyte DDR RAM at 0x0000_0000 21*ebf2b9e3SZubair Lutfullah Kakakhel- 8Kbyte RAM at 0x1000_0000 22*ebf2b9e3SZubair Lutfullah Kakakhel- axi_intc at 0x1020_0000 23*ebf2b9e3SZubair Lutfullah Kakakhel- axi_uart16550 at 0x1040_0000 24*ebf2b9e3SZubair Lutfullah Kakakhel- axi_gpio at 0x1060_0000 25*ebf2b9e3SZubair Lutfullah Kakakhel- axi_i2c at 0x10A0_0000 26*ebf2b9e3SZubair Lutfullah Kakakhel- custom_gpio at 0x10C0_0000 27*ebf2b9e3SZubair Lutfullah Kakakhel- axi_ethernetlite at 0x10E0_0000 28*ebf2b9e3SZubair Lutfullah Kakakhel- 8Kbyte BootRAM at 0x1FC0_0000 29*ebf2b9e3SZubair Lutfullah Kakakhel- 16Mbyte QPI at 0x1D00_0000 30*ebf2b9e3SZubair Lutfullah Kakakhel 31*ebf2b9e3SZubair Lutfullah KakakhelBoot protocol: 32*ebf2b9e3SZubair Lutfullah Kakakhel-------------- 33*ebf2b9e3SZubair Lutfullah Kakakhel 34*ebf2b9e3SZubair Lutfullah KakakhelThe BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000. 35*ebf2b9e3SZubair Lutfullah KakakhelThis is for easy reprogrammibility via JTAG. 36*ebf2b9e3SZubair Lutfullah Kakakhel 37*ebf2b9e3SZubair Lutfullah KakakhelDDR initialization is already handled by a HW IP block. 38*ebf2b9e3SZubair Lutfullah Kakakhel 39*ebf2b9e3SZubair Lutfullah KakakhelWhen the example project bitstream is loaded, the cpu_reset button 40*ebf2b9e3SZubair Lutfullah Kakakhelneeds to be pressed. 41*ebf2b9e3SZubair Lutfullah Kakakhel 42*ebf2b9e3SZubair Lutfullah KakakhelThe bootram initializes the cache and axi_uart 43*ebf2b9e3SZubair Lutfullah KakakhelThen checks if there is anything non 0xffff_ffff at location 0x1D40_0000 44*ebf2b9e3SZubair Lutfullah Kakakhel 45*ebf2b9e3SZubair Lutfullah KakakhelIf there is, then that is considered as u-boot. u-boot is copied from 46*ebf2b9e3SZubair Lutfullah Kakakhel0x1D40_0000 to memory and the bootram jumps into u-boot code. 47*ebf2b9e3SZubair Lutfullah Kakakhel 48*ebf2b9e3SZubair Lutfullah KakakhelAt this point, the board is ready to load the Linux kernel + buildroot initramfs 49*ebf2b9e3SZubair Lutfullah Kakakhel 50*ebf2b9e3SZubair Lutfullah KakakhelThis can be done in multiple ways: 51*ebf2b9e3SZubair Lutfullah Kakakhel 52*ebf2b9e3SZubair Lutfullah Kakakhel1- JTAG load the binary and jump into it. 53*ebf2b9e3SZubair Lutfullah Kakakhel2- Load kernel stored in the QSPI flash at 0x1D80_0000 54*ebf2b9e3SZubair Lutfullah Kakakhel3- Load uImage via tftp. Ethernet works in u-boot. 55*ebf2b9e3SZubair Lutfullah Kakakhel e.g. env set server ip 192.168.154.45; dhcp uImage; bootm 56