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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dhost-generic-pci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
31 While ECAM extends this by 4 bits to accommodate 4k of function space:
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H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
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H A Dpcie-al.txt3 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
5 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
9 - compatible:
13 - "amazon,al-alpine-v2-pcie" for alpine_v2
14 - "amazon,al-alpine-v3-pcie" for alpine_v3
16 - reg:
18 Value type: <prop-encoded-array>
19 Definition: Register ranges as listed in the reg-names property
21 - reg-names:
25 - "config" PCIe ECAM space
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/openbmc/linux/include/linux/
H A Dpci-ecam.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 * Memory address shift values for the byte-level address that
18 * Enhanced Configuration Access Mechanism (ECAM)
21 * Section 7.2.2, Table 7-1, p. 677.
53 * use ECAM.
62 void __iomem *win; /* 64-bit single mapping */
63 void __iomem **winp; /* 32-bit per-bus mapping */
65 struct device *parent;/* ECAM res was from this dev */
74 /* map_bus when ->sysdata is an instance of pci_config_window */
77 /* default ECAM ops */
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/openbmc/u-boot/drivers/pci/
H A DKconfig16 orgnising devices in U-Boot. For PCI, driver model keeps track of
36 Armada37x0 SoCs. The PCIe controller on Armada37x0 is based on
55 bool "Generic ECAM-based PCI host controller support"
59 Say Y here if you want to enable support for generic ECAM-based
63 bool "Enable Armada-8K PCIe driver (DesignWare core)"
68 Armada-8K SoCs. The PCIe controller on Armada-8K is based on
99 support to work (e.g. beaver, jetson-tk1).
H A Dpcie_ecam_generic.c1 // SPDX-License-Identifier: GPL-2.0
5 * Heavily based on drivers/pci/pcie_xilinx.c
17 * struct generic_ecam_pcie - generic_ecam PCIe controller state
25 * pci_generic_ecam_conf_address() - Calculate the address of a config access
44 addr = pcie->cfg_base; in pci_generic_ecam_conf_address()
55 * pci_generic_ecam_read_config() - Read from configuration space
75 * pci_generic_ecam_write_config() - Write to configuration space
95 * pci_generic_ecam_ofdata_to_platdata() - Translate from DT to device state
102 * Return: 0 on success, else -EINVAL
111 err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg", in pci_generic_ecam_ofdata_to_platdata()
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/openbmc/linux/drivers/pci/controller/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
45 system-on-chips, like the Apple M1. This is required for the USB
46 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
63 Broadcom STB based SoCs, like the Raspberry Pi 4.
102 bool "Cavium Thunder PCIe controller to off-chip devices"
110 bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
115 Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
149 in the Intel IXP4xx XScale-based network processor SoC.
185 is used on 32-bit Marvell ARM SoCs: Dove, Kirkwood, Armada 370,
205 multi-function devices.
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H A Dpcie-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
24 #include <linux/pci-ecam.h>
94 * struct xilinx_pcie - PCIe port information
115 return readl(pcie->reg_base + reg); in pcie_read()
120 writel(val, pcie->reg_base + reg); in pcie_write()
130 * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
135 struct device *dev = pcie->dev; in xilinx_pcie_clear_err_interrupts()
147 * xilinx_pcie_valid_device - Check if a valid device is present on bus
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H A Dpcie-xilinx-nwl.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
21 #include <linux/pci-ecam.h>
33 /* Egress - Bridge translation registers */
43 /* Ingress - address translations */
51 /* Rxed msg fifo - Interrupt status registers */
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
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H A Dpci-xgene.c1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene PCIe Driver
19 #include <linux/pci-acpi.h>
20 #include <linux/pci-ecam.h>
74 return readl(port->csr_base + reg); in xgene_pcie_readl()
79 writel(val, port->csr_base + reg); in xgene_pcie_writel()
92 return (struct xgene_pcie *)(bus->sysdata); in pcie_bus_to_port()
94 cfg = bus->sysdata; in pcie_bus_to_port()
95 return (struct xgene_pcie *)(cfg->priv); in pcie_bus_to_port()
106 if (bus->number >= (bus->primary + 1)) in xgene_pcie_get_cfg_base()
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H A Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
138 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
150 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
159 * @imap_addr_offset: register offset between the upper and lower 32-bit
400 struct iproc_pcie *pcie = bus->sysdata; in iproc_data()
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H A Dpci-aardvark.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/pci-ecam.h>
30 #include "../pci-bridge-emul.h"
140 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
295 writel(val, pcie->base + reg); in advk_writel()
300 return readl(pcie->base + reg); in advk_readl()
315 /* check if LTSSM is in normal operation - some L* state */ in advk_pcie_link_up()
323 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_active()
337 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_training()
360 return -ETIMEDOUT; in advk_pcie_wait_for_link()
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H A Dpci-hyperv.c1 // SPDX-License-Identifier: GPL-2.0
8 * This driver acts as a paravirtual front-end for PCI Express root buses.
9 * When a PCI Express function (either an entire device or an SR-IOV
13 * VM within Hyper-V, there may seem to be no PCI bus at all in the VM
18 * to the VM using this front-end will appear at "device 0", the domain will
24 * MSI or MSI-X) associated with the functions on the bus. As interrupts are
28 * vector. This driver does not support level-triggered (line-based)
32 * The rest of this driver mostly maps PCI concepts onto underlying Hyper-V
34 * by Hyper-V is mapped into a single page of memory space, and the
37 * the PCI back-end driver in Hyper-V.
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/openbmc/u-boot/doc/
H A DREADME.qemu-arm1 # SPDX-License-Identifier: GPL-2.0+
5 U-Boot on QEMU's 'virt' machine on ARM & AArch64
9 virtualization purposes. This document describes how to run U-Boot under it.
10 Both 32-bit ARM and AArch64 are supported.
14 - A freely configurable amount of CPU cores
15 - U-Boot loaded and executing in the emulated flash at address 0x0
16 - A generated device tree blob placed at the start of RAM
17 - A freely configurable amount of RAM, described by the DTB
18 - A PL011 serial port, discoverable via the DTB
19 - An ARMv7/ARMv8 architected timer
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/openbmc/qemu/hw/pci-host/
H A Dgpex.c6 * Code loosely based on q35.c.
28 * http://www.kernel.org/doc/Documentation/devicetree/bindings/pci/host-generic-pci.txt
35 #include "hw/pci-host/gpex.h"
36 #include "hw/qdev-properties.h"
48 qemu_set_irq(s->irq[irq_num], level); in gpex_set_irq()
54 return -EINVAL; in gpex_set_irq_num()
57 s->irq_num[index] = gsi; in gpex_set_irq_num()
65 int gsi = s->irq_num[pin]; in gpex_route_intx_pin_to_irq()
86 sysbus_init_mmio(sbd, &pex->mmio); in gpex_host_realize()
101 * addresses read as -1 and ignore writes"; this is traditional in gpex_host_realize()
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/openbmc/u-boot/arch/x86/cpu/qemu/
H A Dqemu.c1 // SPDX-License-Identifier: GPL-2.0+
41 /* the endianness of data register is string-preserving */ in qemu_x86_fwcfg_read_entry_pio()
42 while (size--) in qemu_x86_fwcfg_read_entry_pio()
51 while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR) in qemu_x86_fwcfg_read_entry_dma()
93 * the same bitfield layout. Here we determine the offset based on its in qemu_chipset_init()
127 /* Configure PCIe ECAM base address */ in qemu_chipset_init()
173 * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not in mp_determine_pci_dstirq()
174 * connected to I/O APIC INTPIN#16-19. Instead they are routed in mp_determine_pci_dstirq()
181 * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. in mp_determine_pci_dstirq()
182 * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11]. in mp_determine_pci_dstirq()
/openbmc/qemu/hw/openrisc/
H A Dvirt.c2 * SPDX-License-Identifier: GPL-2.0-or-later
10 #include "qemu/error-report.h"
11 #include "qemu/guest-random.h"
14 #include "exec/address-spaces.h"
17 #include "hw/char/serial-mm.h"
18 #include "hw/core/split-irq.h"
22 #include "hw/pci-host/gpex.h"
23 #include "hw/qdev-properties.h"
26 #include "hw/virtio/virtio-mmio.h"
100 cpu_set_gpr(&cpu->env, 3, boot_info.fdt_addr); in main_cpu_reset()
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/openbmc/u-boot/arch/x86/
H A DKconfig8 prompt "Run U-Boot in 32/64-bit mode"
11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12 even on 64-bit machines. In this case SPL is not used, and U-Boot
13 runs directly from the reset vector (via 16-bit start-up).
15 Alternatively it can be run as a 64-bit binary, thus requiring a
16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17 start-up) then jumps to U-Boot in 64-bit mode.
19 For now, 32-bit mode is recommended, as 64-bit is still
23 bool "32-bit"
25 Build U-Boot as a 32-bit binary with no SPL. This is the currently
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/openbmc/qemu/hw/loongarch/
H A Dvirt.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include "hw/char/serial-mm.h"
21 #include "exec/address-spaces.h"
30 #include "hw/pci-host/ls7a.h"
31 #include "hw/pci-host/gpex.h"
36 #include "hw/acpi/aml-build.h"
37 #include "qapi/qapi-visit-common.h"
42 #include "hw/core/sysbus-fdt.h"
43 #include "hw/platform-bus.h"
45 #include "hw/mem/pc-dimm.h"
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/openbmc/linux/arch/x86/pci/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Low-Level PCI Support for PC
5 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
10 #include <linux/pci-acpi.h>
35 int pcibios_last_bus = -1;
44 return raw_pci_ops->read(domain, bus, devfn, reg, len, val); in raw_pci_read()
46 return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val); in raw_pci_read()
47 return -EINVAL; in raw_pci_read()
54 return raw_pci_ops->write(domain, bus, devfn, reg, len, val); in raw_pci_write()
56 return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val); in raw_pci_write()
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/openbmc/qemu/hw/mips/
H A Dloongson3_virt.c2 * Generic Loongson-3 Platform support
4 * Copyright (c) 2018-2020 Huacai Chen (chenhc@lemote.com)
5 * Copyright (c) 2018-2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
22 * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with
32 #include "hw/char/serial-mm.h"
45 #include "hw/pci-host/gpex.h"
52 #include "qemu/error-report.h"
59 * Loongson-3's virtual machine BIOS can be obtained here:
60 * 1, https://github.com/loongson-community/firmware-nonfree
104 #define TYPE_LOONGSON_MACHINE MACHINE_TYPE_NAME("loongson3-virt")
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/openbmc/qemu/hw/arm/
H A Dvirt.c2 * ARM mach-virt emulation
21 * + we can only present devices whose Linux drivers will work based
23 * + we want to present a very stripped-down minimalist platform,
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
56 #include "qemu/error-report.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
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H A Dvirt-acpi-build.c5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
32 #include "qemu/error-report.h"
35 #include "hw/acpi/acpi-defs.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/acpi/aml-build.h"
49 #include "hw/pci-host/gpex.h"
53 #include "hw/platform-bus.h"
60 #include "hw/virtio/virtio-acpi.h"
72 for (i = 0; i < ms->smp.cpus; i++) { in acpi_dsdt_add_cpus()
88 aml_append(crs, aml_memory32_fixed(uart_memmap->base, in acpi_dsdt_add_uart()
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/openbmc/qemu/hw/riscv/
H A Dvirt.c2 * QEMU RISC-V VirtIO Board
6 * RISC-V machine with 16550a UART and VirtIO MMIO
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial-mm.h"
32 #include "hw/core/sysbus-fdt.h"
45 #include "hw/platform-bus.h"
54 #include "hw/pci-host/gpex.h"
56 #include "hw/acpi/aml-build.h"
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/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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