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/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c3 * sunxi DRAM controller initialization
7 * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
17 * Unfortunately the only documentation we have on the sun7i DRAM
26 #include <asm/arch/dram.h>
54 * This performs the external DRAM reset by driving the RESET pin low and
60 struct sunxi_dram_reg *dram = in mctl_ddr3_reset() local
73 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
75 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
79 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
81 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
[all …]
H A DKconfig12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
114 Select this for sunxi SoCs which uses a DRAM controller like the
116 not have official open-source DRAM initialization code, but can
117 use modified H3 DRAM initialization code.
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/pcie/
H A Dctxt-info.c50 struct iwl_dram_data *dram) in iwl_pcie_ctxt_info_alloc_dma() argument
52 dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len, in iwl_pcie_ctxt_info_alloc_dma()
53 &dram->physical); in iwl_pcie_ctxt_info_alloc_dma()
54 if (!dram->block) in iwl_pcie_ctxt_info_alloc_dma()
57 dram->size = len; in iwl_pcie_ctxt_info_alloc_dma()
58 memcpy(dram->block, data, len); in iwl_pcie_ctxt_info_alloc_dma()
65 struct iwl_self_init_dram *dram = &trans->init_dram; in iwl_pcie_ctxt_info_free_paging() local
68 if (!dram->paging) { in iwl_pcie_ctxt_info_free_paging()
69 WARN_ON(dram->paging_cnt); in iwl_pcie_ctxt_info_free_paging()
74 for (i = 0; i < dram->paging_cnt; i++) in iwl_pcie_ctxt_info_free_paging()
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/openbmc/linux/tools/perf/pmu-events/arch/x86/sandybridge/
H A Dmemory.json113 …on": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.",
115 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
122 …on": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.",
124 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
131 …Description": "Counts all prefetch code reads that miss the LLC and the data returned from dram.",
133 "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM",
140 …Description": "Counts all prefetch data reads that miss the LLC and the data returned from dram.",
142 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM",
149 …"BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.",
151 "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM",
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/openbmc/linux/tools/perf/pmu-events/arch/x86/nehalemex/
H A Dmemory.json3 "BriefDescription": "Offcore data reads satisfied by any DRAM",
21 "BriefDescription": "Offcore data reads satisfied by the local DRAM",
30 "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
39 "BriefDescription": "Offcore code reads satisfied by any DRAM",
57 "BriefDescription": "Offcore code reads satisfied by the local DRAM",
66 "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
75 "BriefDescription": "Offcore requests satisfied by any DRAM",
93 "BriefDescription": "Offcore requests satisfied by the local DRAM",
102 "BriefDescription": "Offcore requests satisfied by a remote DRAM",
111 "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
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/openbmc/linux/tools/perf/pmu-events/arch/x86/westmereex/
H A Dmemory.json10 "BriefDescription": "Offcore data reads satisfied by any DRAM",
28 "BriefDescription": "Offcore data reads satisfied by the local DRAM",
37 "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
46 "BriefDescription": "Offcore code reads satisfied by any DRAM",
64 "BriefDescription": "Offcore code reads satisfied by the local DRAM",
73 "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
82 "BriefDescription": "Offcore requests satisfied by any DRAM",
100 "BriefDescription": "Offcore requests satisfied by the local DRAM",
109 "BriefDescription": "Offcore requests satisfied by a remote DRAM",
118 "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/nehalemep/
H A Dmemory.json3 "BriefDescription": "Offcore data reads satisfied by any DRAM",
21 "BriefDescription": "Offcore data reads satisfied by the local DRAM",
30 "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
39 "BriefDescription": "Offcore code reads satisfied by any DRAM",
57 "BriefDescription": "Offcore code reads satisfied by the local DRAM",
66 "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
75 "BriefDescription": "Offcore requests satisfied by any DRAM",
93 "BriefDescription": "Offcore requests satisfied by the local DRAM",
102 "BriefDescription": "Offcore requests satisfied by a remote DRAM",
111 "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
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/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c3 * LPC32xx dram init
8 * This is called by SPL to gain access to the SDR DRAM.
24 void ddr_init(struct emc_dram_settings *dram) in ddr_init() argument
36 writel(dram->cmddelay, &clk->sdramclk_ctrl); in ddr_init()
37 writel(dram->config0, &emc->config0); in ddr_init()
38 writel(dram->rascas0, &emc->rascas0); in ddr_init()
39 writel(dram->rdconfig, &emc->read_config); in ddr_init()
41 writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); in ddr_init()
42 writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); in ddr_init()
43 writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex); in ddr_init()
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/openbmc/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A Duncore-memory.json3 …ion": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channel…
7 …ion": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channel…
16 …s may merge to a single write command to DRAM. Therefore, the total request count may be higher th…
21 …on": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channel…
25 …on": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channel…
30 …ion": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channel…
34 …ion": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channel…
43 …s may merge to a single write command to DRAM. Therefore, the total request count may be higher th…
48 …on": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channel…
52 …on": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channel…
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/openbmc/linux/tools/perf/pmu-events/arch/x86/westmereep-sp/
H A Dmemory.json3 "BriefDescription": "Offcore data reads satisfied by any DRAM",
21 "BriefDescription": "Offcore data reads satisfied by the local DRAM",
30 "BriefDescription": "Offcore data reads satisfied by a remote DRAM",
39 "BriefDescription": "Offcore code reads satisfied by any DRAM",
57 "BriefDescription": "Offcore code reads satisfied by the local DRAM",
66 "BriefDescription": "Offcore code reads satisfied by a remote DRAM",
75 "BriefDescription": "Offcore requests satisfied by any DRAM",
93 "BriefDescription": "Offcore requests satisfied by the local DRAM",
102 "BriefDescription": "Offcore requests satisfied by a remote DRAM",
111 "BriefDescription": "Offcore RFO requests satisfied by any DRAM",
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/openbmc/u-boot/drivers/ram/aspeed/
H A DKconfig41 bool "bypass self test during DRAM initialization"
44 Say Y here to bypass DRAM self test to speed up the boot time
76 prompt "DDR4 DRAM side ODT"
80 bool "DDR4 DRAM side ODT 80 ohm"
83 select DDR4 DRAM side ODT 80 ohm
86 bool "DDR4 DRAM side ODT 60 ohm"
89 select DDR4 DRAM side ODT 60 ohm
92 bool "DDR4 DRAM side ODT 48 ohm"
95 select DDR4 DRAM side ODT 48 ohm
98 bool "DDR4 DRAM side ODT 40 ohm"
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/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A Ddata-fabric.json36 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
44 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
52 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
60 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
68 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
76 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
84 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
92 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A Ddata-fabric.json36 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
44 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
52 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
60 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
68 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
76 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
84 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
92 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A Ddata-fabric.json36 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
44 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
52 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
60 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
68 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
76 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
84 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
92 …"PublicDescription": "DRAM Channel Controller Request Types: Requests with Data (64B): DRAM Channe…
/openbmc/u-boot/include/dt-bindings/mrc/
H A Dquark.h20 /* If set ODR signal is asserted to DRAM devices on writes */
23 /* DRAM width */
28 /* DRAM speed */
32 /* DRAM type */
36 /* DRAM rank mask */
39 /* DRAM channel mask */
42 /* DRAM channel width */
47 /* DRAM address mode */
52 /* DRAM refresh rate */
57 /* DRAM SR temprature range */
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/openbmc/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-memory.json7 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
17 …"PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-p…
23 "BriefDescription": "DRAM Activate Count : All Activates",
27DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this cha…
32 "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
36DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on…
41 "BriefDescription": "All DRAM CAS commands issued",
45 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
50 "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
54 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A Duncore-memory.json3 …issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data…
11DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. …
19 …issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data…
27 …issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data…
35DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. …
43 …issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data…
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml71 SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
100 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
130 When the DRAM type is DDR3, this parameter defines the ODT disable
132 the ODT on the DRAM side and controller side are both disabled.
138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT
154 When the DRAM type is DDR3, this parameter defines the phy side CA line
162 When the DRAM type is DDR3, this parameter defines the PHY side DQ line
170 When the DRAM type is DDR3, this parameter defines the PHY side ODT
178 When the DRAM type is LPDDR3, this parameter defines then ODT disable
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/openbmc/linux/tools/perf/pmu-events/arch/x86/icelake/
H A Dother.json36 …ounts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the reques…
38 "EventName": "OCR.DEMAND_CODE_RD.DRAM",
45 …ounts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the reques…
63 "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
65 "EventName": "OCR.DEMAND_DATA_RD.DRAM",
72 "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
90 …requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the reques…
92 "EventName": "OCR.DEMAND_RFO.DRAM",
99 …requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the reques…
117 …a cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the reques…
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/openbmc/linux/tools/perf/pmu-events/arch/x86/rocketlake/
H A Dother.json36 …ounts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the reques…
38 "EventName": "OCR.DEMAND_CODE_RD.DRAM",
45 …ounts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the reques…
63 "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
65 "EventName": "OCR.DEMAND_DATA_RD.DRAM",
72 "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
90 …requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the reques…
92 "EventName": "OCR.DEMAND_RFO.DRAM",
99 …requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the reques…
117 …a cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the reques…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A Duncore-memory.json3 …ion": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channel…
7 …tion": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channel…
12DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. …
20 …"BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum o…
24 …"PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all c…
29DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. …
37 "BriefDescription": "ACT command for a read request sent to DRAM",
44 "BriefDescription": "ACT command sent to DRAM",
51 "BriefDescription": "ACT command for a write request sent to DRAM",
58 "BriefDescription": "Read CAS command sent to DRAM",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/alderlaken/
H A Duncore-memory.json3 …ion": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channel…
7 …tion": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channel…
12DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. …
20 …"BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum o…
24 …"PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all c…
29DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. …
37 "BriefDescription": "ACT command for a read request sent to DRAM",
44 "BriefDescription": "ACT command sent to DRAM",
51 "BriefDescription": "ACT command for a write request sent to DRAM",
58 "BriefDescription": "Read CAS command sent to DRAM",
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/openbmc/linux/tools/perf/pmu-events/arch/arm64/freescale/yitian710/sys/
H A Dali_drw.json38 "BriefDescription": "A write data cycle at DFI interface (to DRAM).",
45 "BriefDescription": "A read data cycle at DFI interface (to DRAM).",
73 "BriefDescription": "An Activate(ACT) command to DRAM.",
80 "BriefDescription": "A Read or Write CAS command to DRAM.",
87 "BriefDescription": "An Activate(ACT) command for read to DRAM.",
94 "BriefDescription": "A Read CAS command to DRAM.",
101 "BriefDescription": "A Write CAS command to DRAM.",
108 "BriefDescription": "A Masked Write command to DRAM.",
115 "BriefDescription": "A Precharge(PRE) command to DRAM.",
255 "BriefDescription": "An auto-refresh(REF) command to DRAM.",
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/openbmc/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A Dother.json26 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
28 "EventName": "OCR.DEMAND_CODE_RD.DRAM",
35 …es that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S…
44 …ruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory…
62 "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
64 "EventName": "OCR.DEMAND_DATA_RD.DRAM",
71 …ds that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S…
98 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socke…
116 …"BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory contr…
134 … requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
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/openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Duncore-memory.json3 "BriefDescription": "DRAM Activate Count : All Activates",
7DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this cha…
12 "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
16DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on…
21 "BriefDescription": "All DRAM CAS commands issued",
25 "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
30 "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
34 …"PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issu…
39 "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
43 …ption": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_C…
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