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/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c3 * sunxi DRAM controller initialization
7 * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
17 * Unfortunately the only documentation we have on the sun7i DRAM
26 #include <asm/arch/dram.h>
54 * This performs the external DRAM reset by driving the RESET pin low and
60 struct sunxi_dram_reg *dram = in mctl_ddr3_reset() local
73 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
75 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
79 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
81 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
[all …]
H A DKconfig12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
114 Select this for sunxi SoCs which uses a DRAM controller like the
116 not have official open-source DRAM initialization code, but can
117 use modified H3 DRAM initialization code.
[all …]
H A Ddram_helpers.c3 * DRAM init helper functions
11 #include <asm/arch/dram.h>
22 panic("Timeout initialising DRAM\n"); in mctl_await_completion()
27 * Test if memory at offset offset matches memory at begin of DRAM
/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c3 * LPC32xx dram init
8 * This is called by SPL to gain access to the SDR DRAM.
24 void ddr_init(struct emc_dram_settings *dram) in ddr_init() argument
36 writel(dram->cmddelay, &clk->sdramclk_ctrl); in ddr_init()
37 writel(dram->config0, &emc->config0); in ddr_init()
38 writel(dram->rascas0, &emc->rascas0); in ddr_init()
39 writel(dram->rdconfig, &emc->read_config); in ddr_init()
41 writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); in ddr_init()
42 writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); in ddr_init()
43 writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex); in ddr_init()
[all …]
/openbmc/u-boot/include/dt-bindings/mrc/
H A Dquark.h20 /* If set ODR signal is asserted to DRAM devices on writes */
23 /* DRAM width */
28 /* DRAM speed */
32 /* DRAM type */
36 /* DRAM rank mask */
39 /* DRAM channel mask */
42 /* DRAM channel width */
47 /* DRAM address mode */
52 /* DRAM refresh rate */
57 /* DRAM SR temprature range */
[all …]
/openbmc/u-boot/drivers/ram/aspeed/
H A DKconfig41 bool "bypass self test during DRAM initialization"
44 Say Y here to bypass DRAM self test to speed up the boot time
76 prompt "DDR4 DRAM side ODT"
80 bool "DDR4 DRAM side ODT 80 ohm"
83 select DDR4 DRAM side ODT 80 ohm
86 bool "DDR4 DRAM side ODT 60 ohm"
89 select DDR4 DRAM side ODT 60 ohm
92 bool "DDR4 DRAM side ODT 48 ohm"
95 select DDR4 DRAM side ODT 48 ohm
98 bool "DDR4 DRAM side ODT 40 ohm"
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx5/
H A Dmx53_dram.c15 * to report only the size of the first DRAM bank. This is to make in get_effective_memsize()
17 * end of the first DRAM bank. If we did not override this function in get_effective_memsize()
18 * like so, U-Boot would be placed at the address of the first DRAM in get_effective_memsize()
19 * bank + total DRAM size - sizeof(uboot), which in the setup where in get_effective_memsize()
20 * each DRAM bank contains 512MiB of DRAM would result in placing in get_effective_memsize()
22 * DRAM bank. in get_effective_memsize()
/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A DMakefile5 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
6 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
7 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
8 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
9 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
10 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A DKconfig2 bool "imx8m dram"
17 hex "Define the base address for saved dram timing"
19 after DRAM is trained, need to save the dram related timming
/openbmc/u-boot/arch/x86/include/asm/arch-quark/
H A Dmrc.h29 /* Specify DRAM and channel width */
31 X8, /* DRAM width */
32 X16, /* DRAM width & Channel Width */
36 /* Specify DRAM speed */
42 /* Specify DRAM type */
50 * cl: DRAM CAS Latency in clocks
58 * Refer to JEDEC spec (or DRAM datasheet) when changing these values.
104 * - input parameters like boot mode and DRAM parameters
111 /* DRAM parameters */
176 /* If set ODR signal is asserted to DRAM devices on writes */
/openbmc/u-boot/arch/x86/cpu/quark/
H A Ddram.c79 mrc_params->dram_width = fdtdec_get_int(blob, node, "dram-width", 0); in mrc_configure_params()
80 mrc_params->ddr_speed = fdtdec_get_int(blob, node, "dram-speed", 0); in mrc_configure_params()
81 mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0); in mrc_configure_params()
102 "dram-density", 0); in mrc_configure_params()
103 mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0); in mrc_configure_params()
104 mrc_params->params.ras = fdtdec_get_int(blob, node, "dram-ras", 0); in mrc_configure_params()
105 mrc_params->params.wtr = fdtdec_get_int(blob, node, "dram-wtr", 0); in mrc_configure_params()
106 mrc_params->params.rrd = fdtdec_get_int(blob, node, "dram-rrd", 0); in mrc_configure_params()
107 mrc_params->params.faw = fdtdec_get_int(blob, node, "dram-faw", 0); in mrc_configure_params()
136 /* Set up the DRAM by calling the memory reference code */ in dram_init()
/openbmc/u-boot/arch/x86/dts/
H A Dgalileo.dts51 dram-width = <DRAM_WIDTH_X8>;
52 dram-speed = <DRAM_FREQ_800>;
53 dram-type = <DRAM_TYPE_DDR3>;
63 dram-density = <DRAM_DENSITY_1G>;
64 dram-cl = <6>;
65 dram-ras = <0x0000927c>;
66 dram-wtr = <0x00002710>;
67 dram-rrd = <0x00002710>;
68 dram-faw = <0x00009c40>;
/openbmc/u-boot/include/
H A Dddr_spd.h127 unsigned char psi_ta_dram; /* 48 Thermal Resistance of DRAM Package from
128 Top (Case) to Ambient (Psi T-A DRAM) */
129 unsigned char dt0_mode; /* 49 DRAM Case Temperature Rise from Ambient
132 unsigned char dt2n_dt2q; /* 50 DRAM Case Temperature Rise from Ambient
135 unsigned char dt2p; /* 51 DRAM Case Temperature Rise from Ambient
137 unsigned char dt3n; /* 52 DRAM Case Temperature Rise from Ambient
139 unsigned char dt3pfast; /* 53 DRAM Case Temperature Rise from Ambient
142 unsigned char dt3pslow; /* 54 DRAM Case Temperature Rise from Ambient
145 unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient
148 unsigned char dt5b; /* 56 DRAM Case Temperature Rise from Ambient
[all …]
/openbmc/u-boot/board/xes/xpedite537x/
H A Dddr.c54 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
60 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
66 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
72 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
97 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
103 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
109 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
115 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
133 * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns
134 * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun8i_a33.h3 * Sun8i platform dram controller register and constant defines
84 u32 dramtmg0; /* 0x58 dram timing parameters register 0 */
85 u32 dramtmg1; /* 0x5c dram timing parameters register 1 */
86 u32 dramtmg2; /* 0x60 dram timing parameters register 2 */
87 u32 dramtmg3; /* 0x64 dram timing parameters register 3 */
88 u32 dramtmg4; /* 0x68 dram timing parameters register 4 */
89 u32 dramtmg5; /* 0x6c dram timing parameters register 5 */
90 u32 dramtmg6; /* 0x70 dram timing parameters register 6 */
91 u32 dramtmg7; /* 0x74 dram timing parameters register 7 */
92 u32 dramtmg8; /* 0x78 dram timing parameters register 8 */
[all …]
H A Ddram_sun8i_a83t.h3 * Sun8i platform dram controller register and constant defines
84 u32 dramtmg0; /* 0x58 dram timing parameters register 0 */
85 u32 dramtmg1; /* 0x5c dram timing parameters register 1 */
86 u32 dramtmg2; /* 0x60 dram timing parameters register 2 */
87 u32 dramtmg3; /* 0x64 dram timing parameters register 3 */
88 u32 dramtmg4; /* 0x68 dram timing parameters register 4 */
89 u32 dramtmg5; /* 0x6c dram timing parameters register 5 */
90 u32 dramtmg6; /* 0x70 dram timing parameters register 6 */
91 u32 dramtmg7; /* 0x74 dram timing parameters register 7 */
92 u32 dramtmg8; /* 0x78 dram timing parameters register 8 */
[all …]
/openbmc/u-boot/board/tqc/tqma6/
H A DKconfig17 i.MX6 CPU type and DRAM
23 select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM
29 select TQMa6DL with i.MX6DL and 1GiB DRAM
35 select TQMa6S with i.MX6S and 512 MiB DRAM
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk322x.c363 static void phy_softreset(struct dram_info *dram) in phy_softreset() argument
365 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in phy_softreset()
366 struct rk322x_grf *grf = dram->grf; in phy_softreset()
378 static void set_bw(struct dram_info *dram, u32 bw) in set_bw() argument
380 struct rk322x_ddr_pctl *pctl = dram->chan[0].pctl; in set_bw()
381 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in set_bw()
382 struct rk322x_grf *grf = dram->grf; in set_bw()
577 static void dram_all_config(const struct dram_info *dram, in dram_all_config() argument
595 writel(sys_reg, &dram->grf->os_reg[2]); in dram_all_config()
600 static int dram_cap_detect(struct dram_info *dram, in dram_cap_detect() argument
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/
H A Dmemconf.c33 pr_err("error: unsupported DRAM ch0 width\n"); in __uniphier_memconf_init()
54 pr_err("error: unsupported DRAM ch0 size\n"); in __uniphier_memconf_init()
69 pr_err("error: unsupported DRAM ch1 width\n"); in __uniphier_memconf_init()
90 pr_err("error: unsupported DRAM ch1 size\n"); in __uniphier_memconf_init()
117 pr_err("error: unsupported DRAM ch2 width\n"); in __uniphier_memconf_init()
138 pr_err("error: unsupported DRAM ch2 size\n"); in __uniphier_memconf_init()
/openbmc/u-boot/arch/x86/include/asm/arch-baytrail/fsp/
H A Dfsp_vpd.h21 /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
23 uint8_t dimm_twr; /* tWR in DRAM clk */
24 uint8_t dimm_twtr; /* tWTR in DRAM clk */
25 uint8_t dimm_trrd; /* tRRD in DRAM clk */
26 uint8_t dimm_trtp; /* tRTP in DRAM clk */
27 uint8_t dimm_tfaw; /* tFAW in DRAM clk */
/openbmc/u-boot/arch/arm/mach-rmobile/
H A Dmemmap-gen3.c70 /* Generate entires for DRAM in 32bit address space */ in enable_caches()
75 /* Skip empty DRAM banks */ in enable_caches()
79 /* Skip DRAM above 4 GiB */ in enable_caches()
114 /* Generate entires for DRAM in 64bit address space */ in enable_caches()
119 /* Skip empty DRAM banks */ in enable_caches()
123 /* Skip DRAM below 4 GiB */ in enable_caches()
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg25 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
103 # bit0: 0, DRAM DLL enabled
104 # bit1: 0, DRAM drive strength normal
111 # bit12: 0, DRAM output buffer enabled
161 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
162 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
164 # bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
165 # bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
174 # bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1
175 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
/openbmc/u-boot/drivers/mmc/
H A Dmv_sdhci.c16 const struct mbus_dram_target_info *dram; in sdhci_mvebu_mbus_config() local
19 dram = mvebu_mbus_dram_info(); in sdhci_mvebu_mbus_config()
26 for (i = 0; i < dram->num_cs; i++) { in sdhci_mvebu_mbus_config()
27 const struct mbus_dram_window *cs = dram->cs + i; in sdhci_mvebu_mbus_config()
31 (dram->mbus_dram_target_id << 4) | 1, in sdhci_mvebu_mbus_config()
/openbmc/u-boot/board/sunxi/
H A Ddram_sun5i_auto.c1 /* DRAM parameters for auto dram configuration on sun5i and sun7i */
4 #include <asm/arch/dram.h>
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg112 # bit0: 0, DRAM DLL enabled
113 # bit1: 1, DRAM drive strength reduced
120 # bit12: 0, DRAM output buffer enabled
179 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
180 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
183 # bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1
194 # bit3-0: 0b1111, internal ODT is asserted during read from DRAM bank 0-3
195 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3

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