xes/xpedite537x/ddr.c

54  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
60  *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
66  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
72  *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
97  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
103  *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
109  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
115  *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
133  *      Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 =  0.342ns
134  *      Ch. 0 8572 to DRAM propagation (CLKs) :     2.3" * 180 =  0.414ns
135  *      Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 =  0.126ns
136  *      Ch. 1 8572 to DRAM propagation (CLKs   ) : 1.47" * 180 =  0.264ns