3  * LPC32xx dram init
8  * This is called by SPL to gain access to the SDR DRAM.
24 void ddr_init(struct emc_dram_settings *dram)  in ddr_init()  argument
36 	writel(dram->cmddelay, &clk->sdramclk_ctrl);  in ddr_init()
37 	writel(dram->config0, &emc->config0);  in ddr_init()
38 	writel(dram->rascas0, &emc->rascas0);  in ddr_init()
39 	writel(dram->rdconfig, &emc->read_config);  in ddr_init()
41 	writel((ck / dram->trp) & 0x0000000F, &emc->t_rp);  in ddr_init()
42 	writel((ck / dram->tras) & 0x0000000F, &emc->t_ras);  in ddr_init()
43 	writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex);  in ddr_init()
44 	writel((ck / dram->twr) & 0x0000000F, &emc->t_wr);  in ddr_init()
45 	writel((ck / dram->trc) & 0x0000001F, &emc->t_rc);  in ddr_init()
46 	writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc);  in ddr_init()
47 	writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr);  in ddr_init()
48 	writel(dram->trrd, &emc->t_rrd);  in ddr_init()
49 	writel(dram->tmrd, &emc->t_mrd);  in ddr_init()
50 	writel(dram->tcdlr, &emc->t_cdlr);  in ddr_init()
52 	writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);  in ddr_init()
63 	writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);  in ddr_init()
67 	readl(EMC_DYCS0_BASE | dram->mode);  in ddr_init()
70 	readl(EMC_DYCS0_BASE | dram->emode);  in ddr_init()