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Searched full:dqs (Results 1 – 25 of 177) sorted by relevance

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/openbmc/u-boot/board/gateworks/gw_ventana/
H A Dgw_ventana_spl.c211 /* Read DQS Gating calibration */
214 /* Read Calibration: DQS delay relative to DQ read access */
216 /* Write Calibration: DQ/DM delay relative to DQS write access */
227 /* Read DQS Gating calibration */
232 /* Read Calibration: DQS delay relative to DQ read access */
235 /* Write Calibration: DQ/DM delay relative to DQS write access */
247 /* Read DQS Gating calibration */
252 /* Read Calibration: DQS delay relative to DQ read access */
255 /* Write Calibration: DQ/DM delay relative to DQS write access */
264 /* Read DQS Gating calibration */
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/openbmc/u-boot/arch/mips/mach-mt7620/
H A Dddr_calibrate.c83 static inline int test_loop(int k, int dqs, u32 test_dqs, u32 *coarse_dqs, in test_loop() argument
100 if (dqs > 0) in test_loop()
102 (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 12) | in test_loop()
107 (((k == 1) ? coarse_dqs[dqs] : test_dqs) << 4) | in test_loop()
142 int dqs = 0; in ddr_calibrate() local
180 dqs = 0; in ddr_calibrate()
182 /* Add by KP, DQS MIN boundary */ in ddr_calibrate()
195 /* DQS MIN boundary */ in ddr_calibrate()
208 flag = test_loop(k, dqs, test_dqs, max_coarse_dqs, in ddr_calibrate()
217 max_coarse_dqs[dqs] = test_dqs; in ddr_calibrate()
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dqs.c125 * Desc: Execute the DQS centralization RX phase.
135 DEBUG_DQS_S("DDR3 - DQS Centralization RX - Starting procedure\n"); in ddr3_dqs_centralization_rx()
144 DEBUG_DQS_S("DDR3 - DQS Centralization RX - SW Override Enabled\n"); in ddr3_dqs_centralization_rx()
152 DEBUG_DQS_FULL_C("DDR3 - DQS Centralization RX - CS - ", in ddr3_dqs_centralization_rx()
165 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - ECC Mux Enabled\n"); in ddr3_dqs_centralization_rx()
167 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - ECC Mux Disabled\n"); in ddr3_dqs_centralization_rx()
169 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - Find all limits\n"); in ddr3_dqs_centralization_rx()
176 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - Start calculating center\n"); in ddr3_dqs_centralization_rx()
207 * Desc: Execute the DQS centralization TX phase.
217 DEBUG_DQS_S("DDR3 - DQS Centralization TX - Starting procedure\n"); in ddr3_dqs_centralization_tx()
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H A Dddr3_pbs.c171 /* Clear the locked DQs */ in ddr3_pbs_tx()
327 /* Loop for all dqs */ in ddr3_pbs_tx()
472 DEBUG_PBS_FULL_S("Shift DQS by 2 steps for PUPs: "); in ddr3_tx_shift_dqs_adll_step_before_fail()
503 /* Set the PUP DQS DLY Values */ in ddr3_tx_shift_dqs_adll_step_before_fail()
613 /* Clear the locked DQs */ in ddr3_pbs_rx()
651 /* Set all DQS PBS values to MIN (0) */ in ddr3_pbs_rx()
661 /* Shift DQS, To first Fail */ in ddr3_pbs_rx()
662 DEBUG_PBS_FULL_S("DDR3 - PBS Rx - Shift RX DQS to first fail\n"); in ddr3_pbs_rx()
745 /* Return DQS ADLL to default value - 15 */ in ddr3_pbs_rx()
746 /* Set all DQS PBS values to MIN (0) */ in ddr3_pbs_rx()
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H A Dddr3_axp_training_static.h56 /*center DQS on read cycle */
129 /*center DQS on read cycle */
183 /*center DQS on read cycle */
236 /*center DQS on read cycle */
289 /*center DQS on read cycle */
342 /*center DQS on read cycle */
396 /*center DQS on read cycle */
449 /*center DQS on read cycle */
502 /*center DQS on read cycle */
555 /*center DQS on read cycle */
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H A Dddr3_axp_config.h15 * Level 2: Provides the windows margin as a results of DQS centeralization
16 * Level 3: Provides the windows margin of each DQ as a results of DQS
40 * DQS_CLK_ALIGNED - Set this if CLK and DQS signals are aligned on board
H A Dddr3_write_leveling.c104 * High freq Supplement and DQS Centralization in ddr3_write_leveling_hw()
128 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw()
291 /* Check pup which DQS/DATA is error */ in ddr3_wl_supplement()
342 /* clock is longer than DQS */ in ddr3_wl_supplement()
356 DEBUG_WL_S("#### Clock is longer than DQS more than one clk cycle ####\n"); in ddr3_wl_supplement()
363 /* clock is align to DQS */ in ddr3_wl_supplement()
377 DEBUG_WL_S("#### Warning - Possible Layout Violation (DQS is longer than CLK)####\n"); in ddr3_wl_supplement()
428 * Read results to arrays - Results are required for DQS Centralization in ddr3_wl_supplement()
527 * freq Supplement and DQS Centralization in ddr3_write_leveling_hw_reg_dimm()
564 dram_info->wl_val[cs][pup][DQS] = in ddr3_write_leveling_hw_reg_dimm()
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H A Dddr3_axp_mc_static.h43 {0x000014C4, 0x092434e9}, /* DRAM Data and DQS Driving Strenght */
101 {0x000014C4, 0x092434e9}, /* DRAM Data and DQS Driving Strenght */
153 {0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
210 {0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
259 {0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */
/openbmc/u-boot/drivers/ddr/altera/
H A Dsequencer.c341 /* load up dqs config settings */
342 static void scc_mgr_load_dqs(u32 dqs) in scc_mgr_load_dqs() argument
344 writel(dqs, &sdr_scc_mgr->dqs_ena); in scc_mgr_load_dqs()
347 /* load up dqs io config settings */
451 * by the DQS logic block which is instantiated once per read group. in scc_mgr_set_oct_out1_delay()
468 * bits: 0:0 = 1'b1 - DQS bypass in scc_mgr_set_hhp_extras()
489 * scc_mgr_zero_all() - Zero all DQS config
491 * Zero all DQS config.
498 * USER Zero all DQS config settings, across all groups and all in scc_mgr_zero_all()
521 /* Multicast to all DQS group enables. */ in scc_mgr_zero_all()
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/openbmc/u-boot/board/xes/xpedite537x/
H A Dddr.c54 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
60 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
66 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
72 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
97 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
103 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
109 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
115 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
127 * The DDR SDRAM specification requires DQS be received no sooner than
138 * Difference in arrival time CLK vs. DQS:
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/openbmc/u-boot/board/tbs/tbs2910/
H A Dtbs2910.cfg41 /* disable dqs pullup */
52 /* set ddr input mode for dqs signals */
58 /* dqs write delay */
63 /* dqs read delay */
72 /* dqs read gating control */
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dlpddr2.h57 #define MMDC_MPDGCTRL0_MODULE0_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */
58 #define MMDC_MPDGCTRL1_MODULE0_VALUE 0x00000000 /* Read DQS gating control 1 */
62 #define MMDC_MPDGCTRL0_MODULE1_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */
63 #define MMDC_MPDGCTRL1_MODULE1_VALUE 0x00000000 /* Read DQS gating control 1 */
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c356 * bits [31:26] - DQS gating system latency for byte lane 3
357 * bits [25:24] - DQS gating phase select for byte lane 3
358 * bits [23:18] - DQS gating system latency for byte lane 2
359 * bits [17:16] - DQS gating phase select for byte lane 2
360 * bits [15:10] - DQS gating system latency for byte lane 1
361 * bits [ 9:8 ] - DQS gating phase select for byte lane 1
362 * bits [ 7:2 ] - DQS gating system latency for byte lane 0
363 * bits [ 1:0 ] - DQS gating phase select for byte lane 0
654 /* disable drift compensation and set passive DQS window mode */ in dramc_init_helper()
668 /* Hardware DQS gate training */ in dramc_init_helper()
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/openbmc/u-boot/arch/mips/mach-ath79/ar933x/
H A Dddr.c166 /* OCD exit, Enable DLL, Enable /DQS, Reduced Drive Strength */ in ddr_init()
179 /* DQS 0 Tap Control */ in ddr_init()
182 /* DQS 1 Tap Control */ in ddr_init()
223 /* DQS 0 Tap Control */ in ddr_init()
226 /* DQS 1 Tap Control */ in ddr_init()
/openbmc/u-boot/board/bachmann/ot1200/
H A Dot1200_spl.c110 /* Read DQS Gating calibration */
115 /* Read Calibration: DQS delay relative to DQ read access */
118 /* Write Calibration: DQ/DM delay relative to DQS write access */
/openbmc/u-boot/arch/arm/mach-imx/
H A Dddrmc-vf610-calibration.c50 * - 0x2 (b'10) - RDLVL_DL_0/1 - refers to adjusting the DQS strobe in relation
55 * the Read DQS strobe pad from the time that the
148 debug("RDLVL: DQS to DQ (RDLVL)\n"); in ddrmc_cal_dqs_to_dq()
252 debug("RDLVL: The DQS to DQ delay cannot be found!\n"); in ddrmc_cal_dqs_to_dq()
304 debug("RDLVL: The DQS to DQ delay cannot be found!\n"); in ddrmc_cal_dqs_to_dq()
/openbmc/u-boot/board/barco/platinum/
H A Dspl_picon.c105 /* Read DQS Gating calibration */
108 /* Read Calibration: DQS delay relative to DQ read access */
110 /* Write Calibration: DQ/DM delay relative to DQS write access */
H A Dspl_titanium.c104 /* Read DQS Gating calibration */
109 /* Read Calibration: DQS delay relative to DQ read access */
112 /* Write Calibration: DQ/DM delay relative to DQS write access */
/openbmc/u-boot/arch/arm/mach-uniphier/dram/
H A Dddrphy-training.c41 /* Use Multi-Purpose Register for DQS gate training */ in ddrphy_prepare_training()
70 "Read DQS Gate Training",
H A Dddrphy-regs.h24 #define PHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
44 #define PHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
52 #define PHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
H A Dddrmphy-regs.h25 #define MPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
48 #define MPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
56 #define MPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
/openbmc/linux/fs/xfs/
H A Dxfs_trans_dquot.c89 oqa = otp->t_dqinfo->dqs[j]; in xfs_trans_dup_dqinfo()
90 nqa = ntp->t_dqinfo->dqs[j]; in xfs_trans_dup_dqinfo()
157 qa = tp->t_dqinfo->dqs[XFS_QM_TRANS_USR]; in xfs_trans_get_dqtrx()
160 qa = tp->t_dqinfo->dqs[XFS_QM_TRANS_GRP]; in xfs_trans_get_dqtrx()
163 qa = tp->t_dqinfo->dqs[XFS_QM_TRANS_PRJ]; in xfs_trans_get_dqtrx()
347 qa = tp->t_dqinfo->dqs[j]; in xfs_trans_apply_dquot_deltas()
488 qa = tp->t_dqinfo->dqs[j]; in xfs_trans_unreserve_and_mod_dquots()
/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc-exynos.c249 u32 dqs, strobe; in dw_mci_exynos_config_hs400() local
263 dqs = priv->saved_dqs_en; in dw_mci_exynos_config_hs400()
267 dqs |= DATA_STROBE_EN; in dw_mci_exynos_config_hs400()
270 dqs &= 0xffffff00; in dw_mci_exynos_config_hs400()
272 dqs &= ~DATA_STROBE_EN; in dw_mci_exynos_config_hs400()
275 mci_writel(host, HS400_DQS_EN, dqs); in dw_mci_exynos_config_hs400()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun4i.h28 u32 rdgr0; /* 0x5c rank dqs gating register */
29 u32 rdgr1; /* 0x60 rank dqs gating register */
54 u32 dqstr; /* 0x228 dqs timing register */
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr2-timings.yaml35 DQS output data access time from CK_t/CK_c in pico seconds.
40 DQS output data access time from CK_t/CK_c, temperature de-rated, in pico

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