104 		 * High freq Supplement and DQS Centralization  in ddr3_write_leveling_hw()
128 					dram_info->wl_val[cs][pup][DQS] =  in ddr3_write_leveling_hw()
291 					/* Check pup which DQS/DATA is error */  in ddr3_wl_supplement()
342 							/* clock is longer than DQS */  in ddr3_wl_supplement()
356 							DEBUG_WL_S("#### Clock is longer than DQS more than one clk cycle ####\n");  in ddr3_wl_supplement()
363 							/* clock is align to DQS */  in ddr3_wl_supplement()
377 								DEBUG_WL_S("#### Warning - Possible Layout Violation (DQS is longer than CLK)####\n");  in ddr3_wl_supplement()
428 	 * Read results to arrays - Results are required for DQS Centralization  in ddr3_wl_supplement()
527 		 * freq Supplement and DQS Centralization  in ddr3_write_leveling_hw_reg_dimm()
564 					dram_info->wl_val[cs][pup][DQS] =  in ddr3_write_leveling_hw_reg_dimm()
1183 	/* Broadcast to all PUPs: Reset DQS phase, reset leveling delay */  in ddr3_write_leveling_single_cs()
1189 	/* Drive DQS high for one cycle - All data PUPs */  in ddr3_write_leveling_single_cs()
1190 	DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge - Driving DQS high for one cycle\n");  in ddr3_write_leveling_single_cs()
1218 	DEBUG_WL_FULL_S("DDR3 - Write Leveling Single Cs - Seek Edge - Shift DQS + Octet Leveling\n");  in ddr3_write_leveling_single_cs()
1220 	/* Shift DQS + Octet leveling */  in ddr3_write_leveling_single_cs()
1223 			/*  Broadcast to all PUPs: DQS phase,leveling delay */  in ddr3_write_leveling_single_cs()
1235 			/* Drive DQS high for one cycle - All data PUPs */  in ddr3_write_leveling_single_cs()