1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4 * Based on Atheros LSDK/QSDK
5 */
6
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/addrspace.h>
10 #include <asm/types.h>
11 #include <mach/ar71xx_regs.h>
12 #include <mach/ath79.h>
13
14 #define DDR_CTRL_UPD_EMR3S BIT(5)
15 #define DDR_CTRL_UPD_EMR2S BIT(4)
16 #define DDR_CTRL_PRECHARGE BIT(3)
17 #define DDR_CTRL_AUTO_REFRESH BIT(2)
18 #define DDR_CTRL_UPD_EMRS BIT(1)
19 #define DDR_CTRL_UPD_MRS BIT(0)
20
21 #define DDR_REFRESH_EN BIT(14)
22 #define DDR_REFRESH_M 0x3ff
23 #define DDR_REFRESH(x) ((x) & 0x3ff)
24 #define DDR_REFRESH_VAL_25M (DDR_REFRESH_EN | DDR_REFRESH(390))
25 #define DDR_REFRESH_VAL_40M (DDR_REFRESH_EN | DDR_REFRESH(624))
26
27 #define DDR_TRAS_S 0
28 #define DDR_TRAS_M 0x1f
29 #define DDR_TRAS(x) ((x) << DDR_TRAS_S)
30 #define DDR_TRCD_M 0xf
31 #define DDR_TRCD_S 5
32 #define DDR_TRCD(x) ((x) << DDR_TRCD_S)
33 #define DDR_TRP_M 0xf
34 #define DDR_TRP_S 9
35 #define DDR_TRP(x) ((x) << DDR_TRP_S)
36 #define DDR_TRRD_M 0xf
37 #define DDR_TRRD_S 13
38 #define DDR_TRRD(x) ((x) << DDR_TRRD_S)
39 #define DDR_TRFC_M 0x7f
40 #define DDR_TRFC_S 17
41 #define DDR_TRFC(x) ((x) << DDR_TRFC_S)
42 #define DDR_TMRD_M 0xf
43 #define DDR_TMRD_S 23
44 #define DDR_TMRD(x) ((x) << DDR_TMRD_S)
45 #define DDR_CAS_L_M 0x17
46 #define DDR_CAS_L_S 27
47 #define DDR_CAS_L(x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
48 #define DDR_OPEN BIT(30)
49 #define DDR_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \
50 DDR_TRP(6) | DDR_TRRD(4) | \
51 DDR_TRFC(30) | DDR_TMRD(15) | \
52 DDR_CAS_L(7) | DDR_OPEN)
53
54 #define DDR_BURST_LEN_S 0
55 #define DDR_BURST_LEN_M 0xf
56 #define DDR_BURST_LEN(x) ((x) << DDR_BURST_LEN_S)
57 #define DDR_BURST_TYPE BIT(4)
58 #define DDR_CNTL_OE_EN BIT(5)
59 #define DDR_PHASE_SEL BIT(6)
60 #define DDR_CKE BIT(7)
61 #define DDR_TWR_S 8
62 #define DDR_TWR_M 0xf
63 #define DDR_TWR(x) ((x) << DDR_TWR_S)
64 #define DDR_TRTW_S 12
65 #define DDR_TRTW_M 0x1f
66 #define DDR_TRTW(x) ((x) << DDR_TRTW_S)
67 #define DDR_TRTP_S 17
68 #define DDR_TRTP_M 0xf
69 #define DDR_TRTP(x) ((x) << DDR_TRTP_S)
70 #define DDR_TWTR_S 21
71 #define DDR_TWTR_M 0x1f
72 #define DDR_TWTR(x) ((x) << DDR_TWTR_S)
73 #define DDR_G_OPEN_L_S 26
74 #define DDR_G_OPEN_L_M 0xf
75 #define DDR_G_OPEN_L(x) ((x) << DDR_G_OPEN_L_S)
76 #define DDR_HALF_WIDTH_LOW BIT(31)
77 #define DDR_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
78 DDR_CKE | DDR_TWR(6) | DDR_TRTW(14) | \
79 DDR_TRTP(8) | DDR_TWTR(14) | \
80 DDR_G_OPEN_L(7) | DDR_HALF_WIDTH_LOW)
81
82 #define DDR2_CONF_TWL_S 10
83 #define DDR2_CONF_TWL_M 0xf
84 #define DDR2_CONF_TWL(x) (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
85 #define DDR2_CONF_ODT BIT(9)
86 #define DDR2_CONF_TFAW_S 2
87 #define DDR2_CONF_TFAW_M 0x3f
88 #define DDR2_CONF_TFAW(x) (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
89 #define DDR2_CONF_EN BIT(0)
90 #define DDR2_CONF_VAL (DDR2_CONF_TWL(2) | DDR2_CONF_ODT | \
91 DDR2_CONF_TFAW(22) | DDR2_CONF_EN)
92
93 #define DDR1_EXT_MODE_VAL 0x02
94 #define DDR2_EXT_MODE_VAL 0x402
95 #define DDR2_EXT_MODE_OCD_VAL 0x382
96 #define DDR1_MODE_DLL_VAL 0x133
97 #define DDR2_MODE_DLL_VAL 0x100
98 #define DDR1_MODE_VAL 0x33
99 #define DDR2_MODE_VAL 0xa33
100 #define DDR_TAP_VAL0 0x08
101 #define DDR_TAP_VAL1 0x09
102
ddr_init(void)103 void ddr_init(void)
104 {
105 void __iomem *regs;
106 u32 val;
107
108 regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
109 MAP_NOCACHE);
110
111 writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
112 writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
113
114 val = ath79_get_bootstrap();
115 if (val & AR933X_BOOTSTRAP_DDR2) {
116 /* AHB maximum timeout */
117 writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
118
119 /* Enable DDR2 */
120 writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG);
121
122 /* Precharge All */
123 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
124
125 /* Disable High Temperature Self-Refresh, Full Array */
126 writel(0x00, regs + AR933X_DDR_REG_EMR2);
127
128 /* Extended Mode Register 2 Set (EMR2S) */
129 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
130
131 writel(0x00, regs + AR933X_DDR_REG_EMR3);
132
133 /* Extended Mode Register 3 Set (EMR3S) */
134 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
135
136 /* Enable DLL, Full strength, ODT Disabled */
137 writel(0x00, regs + AR71XX_DDR_REG_EMR);
138
139 /* Extended Mode Register Set (EMRS) */
140 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
141
142 /* Reset DLL */
143 writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
144
145 /* Mode Register Set (MRS) */
146 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
147
148 /* Precharge All */
149 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
150
151 /* Auto Refresh */
152 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
153 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
154
155 /* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */
156 writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
157 /* Mode Register Set (MRS) */
158 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
159
160 /* Enable OCD defaults, Enable DLL, Reduced Drive Strength */
161 writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
162
163 /* Extended Mode Register Set (EMRS) */
164 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
165
166 /* OCD exit, Enable DLL, Enable /DQS, Reduced Drive Strength */
167 writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
168 /* Extended Mode Register Set (EMRS) */
169 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
170
171 /* Refresh time control */
172 if (val & AR933X_BOOTSTRAP_REF_CLK_40)
173 writel(DDR_REFRESH_VAL_40M, regs +
174 AR71XX_DDR_REG_REFRESH);
175 else
176 writel(DDR_REFRESH_VAL_25M, regs +
177 AR71XX_DDR_REG_REFRESH);
178
179 /* DQS 0 Tap Control */
180 writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
181
182 /* DQS 1 Tap Control */
183 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
184
185 /* For 16-bit DDR */
186 writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
187 } else {
188 /* AHB maximum timeout */
189 writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
190
191 /* Precharge All */
192 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
193
194 /* Reset DLL, Burst Length 8, CAS Latency 3 */
195 writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
196
197 /* Forces an MRS update cycle in DDR */
198 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
199
200 /* Enable DLL, Full strength */
201 writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
202
203 /* Extended Mode Register Set (EMRS) */
204 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
205
206 /* Precharge All */
207 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
208
209 /* Normal DLL, Burst Length 8, CAS Latency 3 */
210 writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
211
212 /* Mode Register Set (MRS) */
213 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
214
215 /* Refresh time control */
216 if (val & AR933X_BOOTSTRAP_REF_CLK_40)
217 writel(DDR_REFRESH_VAL_40M, regs +
218 AR71XX_DDR_REG_REFRESH);
219 else
220 writel(DDR_REFRESH_VAL_25M, regs +
221 AR71XX_DDR_REG_REFRESH);
222
223 /* DQS 0 Tap Control */
224 writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
225
226 /* DQS 1 Tap Control */
227 writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
228
229 /* For 16-bit DDR */
230 writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
231 }
232 }
233
ddr_tap_tuning(void)234 void ddr_tap_tuning(void)
235 {
236 void __iomem *regs;
237 u32 *addr_k0, *addr_k1, *addr;
238 u32 val, tap, upper, lower;
239 int i, j, dir, err, done;
240
241 regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
242 MAP_NOCACHE);
243
244 /* Init memory pattern */
245 addr = (void *)CKSEG0ADDR(0x2000);
246 for (i = 0; i < 256; i++) {
247 val = 0;
248 for (j = 0; j < 8; j++) {
249 if (i & (1 << j)) {
250 if (j % 2)
251 val |= 0xffff0000;
252 else
253 val |= 0x0000ffff;
254 }
255
256 if (j % 2) {
257 *addr++ = val;
258 val = 0;
259 }
260 }
261 }
262
263 err = 0;
264 done = 0;
265 dir = 1;
266 tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
267 val = tap;
268 upper = tap;
269 lower = tap;
270 while (!done) {
271 err = 0;
272
273 /* Update new DDR tap value */
274 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
275 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
276
277 /* Compare DDR with cache */
278 for (i = 0; i < 2; i++) {
279 addr_k1 = (void *)CKSEG1ADDR(0x2000);
280 addr_k0 = (void *)CKSEG0ADDR(0x2000);
281 addr = (void *)CKSEG0ADDR(0x3000);
282
283 while (addr_k0 < addr) {
284 if (*addr_k1++ != *addr_k0++) {
285 err = 1;
286 break;
287 }
288 }
289
290 if (err)
291 break;
292 }
293
294 if (err) {
295 /* Save upper/lower threshold if error */
296 if (dir) {
297 dir = 0;
298 val--;
299 upper = val;
300 val = tap;
301 } else {
302 val++;
303 lower = val;
304 done = 1;
305 }
306 } else {
307 /* Try the next value until limitation */
308 if (dir) {
309 if (val < 0x20) {
310 val++;
311 } else {
312 dir = 0;
313 upper = val;
314 val = tap;
315 }
316 } else {
317 if (!val) {
318 lower = val;
319 done = 1;
320 } else {
321 val--;
322 }
323 }
324 }
325 }
326
327 /* compute an intermediate value and write back */
328 val = (upper + lower) / 2;
329 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
330 val++;
331 writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
332 }
333