Lines Matching full:dqs

54  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
60  *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
66  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
72  *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
97  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
103  *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
109  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
115  *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
127  *      The DDR SDRAM specification requires DQS be received no sooner than
138  * Difference in arrival time CLK vs. DQS:
144  *      the 1/2 cycle which normally aligns the first DQS transition