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/openbmc/u-boot/cmd/
H A Dtime.c9 static void report_time(ulong cycles) in report_time() argument
14 total_seconds = cycles / CONFIG_SYS_HZ; in report_time()
15 remainder = cycles % CONFIG_SYS_HZ; in report_time()
29 ulong cycles = 0; in do_time() local
36 retval = cmd_process(0, argc - 1, argv + 1, &repeatable, &cycles); in do_time()
37 report_time(cycles); in do_time()
/openbmc/u-boot/arch/sh/lib/
H A Dudivsi3_i4i-Os.S12 udiv small divisor: 55 cycles
13 udiv large divisor: 52 cycles
14 sdiv small divisor, positive result: 59 cycles
15 sdiv large divisor, positive result: 56 cycles
16 sdiv small divisor, negative result: 65 cycles (*)
17 sdiv large divisor, negative result: 62 cycles (*)
19 of two more cycles. */
/openbmc/u-boot/board/armltd/integrator/
H A Darm-ebi.h21 * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
/openbmc/u-boot/arch/xtensa/lib/
H A Dtime.c24 static void delay_cycles(unsigned cycles) in delay_cycles() argument
27 unsigned expiry = get_ccount() + cycles; in delay_cycles()
39 for (i = cycles >> 4U; i > 0; --i) in delay_cycles()
41 fake_ccount += cycles; in delay_cycles()
78 * Add at least the overhead of this call (in cycles). in get_timer()
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg118 DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1)
119 # bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles
120 # bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles
121 # bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles
122 # bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
123 # bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
126 # bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
127 # bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
130 # bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles
196 # bit 7-4: 2, M_ODT assertion 2 cycles after read start command
[all …]
H A Dkwbimage-memphis.cfg65 DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
133 # bit7-4 : 0010, M_ODT assertion 2 cycles after read
134 # bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
135 # bit15-12: 0100, internal ODT assertion 4 cycles after read
136 # bit19-16: 1000, internal ODT de-assertion 8 cycles after read
141 # bit7-4 : 0101, M_ODT de-assertion x cycles after write
142 # bit11-8 : 0100, internal ODT assertion x cycles after write
143 # bit15-12: 1000, internal ODT de-assertion x cycles after write
H A Dkwbimage_128M16_1.cfg118 DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1)
196 # bit 7-4: 2, M_ODT assertion 2 cycles after read start command
197 # bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
198 # (ODT turn off delay 2,5 clk cycles)
208 # bit 11-8: 4, internal ODT assertion 2 cycles after write start command
210 # bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
/openbmc/u-boot/include/configs/
H A Dkmp204x.h42 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
44 | OR_GPCM_EAD) /* extra bus clk cycles */
64 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
66 | OR_GPCM_EAD) /* extra bus clk cycles */
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lsxhl.cfg38 # bit4: 1, T2 mode, addr/cmd are driven for two cycles
139 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
140 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
141 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
147 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
148 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
H A Dkwbimage-lschl.cfg139 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
140 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
141 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
147 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
148 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
149 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dabb.c30 * clock cycles that match a given wall time profiled for the ldo. in abb_setup_timings()
33 * of clock cycles per SYS_CLK period (varies per OMAP family), in abb_setup_timings()
39 * (# system clock cycles) * (sys_clk period) in abb_setup_timings()
43 * SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate)) in abb_setup_timings()
45 * To avoid dividing by zero multiply both "# clock cycles" and in abb_setup_timings()
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg128 # bit7-4: 2, 2 cycles from read command to assertion of M_ODT signal
129 # bit11-8: 5, 5 cycles from read command to de-assertion of M_ODT signal
130 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
131 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
135 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
136 # bit7-4: 5, 5 cycles from write command to de-assertion of M_ODT signal
137 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
138 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
/openbmc/qemu/docs/spin/
H A Dtcg-exclusive.promela45 # warning defaulting to 2 CPU cycles
48 # warning defaulting to 1 CPU cycles
185 byte cycles = 0;
189 :: cycles == N_CYCLES -> break;
191 cycles++;
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsys_proto.h20 * Data RAM write latency: 2 cycles in configure_l2ctlr()
21 * Data RAM read latency: 2 cycles in configure_l2ctlr()
/openbmc/phosphor-pid-control/pid/
H A Dpidloop.cpp129 // Process thermal cycles at a rate that is less often than fan in pidControlLoop()
130 // cycles. If thermal time is not an exact multiple of fan time, in pidControlLoop()
151 // to perform thermal cycles, in proper ratio with fan cycles. in pidControlLoop()
/openbmc/u-boot/board/freescale/m5249evb/
H A Dm5249evb.c57 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles) in dram_init()
76 udelay(0x10); /* Allow several Precharge cycles */ in dram_init()
80 udelay(0x7d0); /* Allow gobs of refresh cycles */ in dram_init()
/openbmc/u-boot/board/ccv/xpress/
H A Dspl.c59 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
60 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
62 .refsel = 1, /* Refresh cycles at 32KHz */
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/State/Boot/
H A DPostCode.interface.yaml9 It is used to indicate number of boot cycles that have post codes
14 The max cached boot cycles for post code. It is used to indicate end
/openbmc/u-boot/drivers/pwm/
H A Dpwm-imx.c44 /* set duty cycles */ in pwm_config()
46 /* set period cycles */ in pwm_config()
/openbmc/u-boot/board/mpr2/
H A Dmpr2.c26 __raw_writel(0x36db0400, CS2BCR); /* 4 idle cycles, normal space, 16 bit data bus */ in board_init()
30 __raw_writel(0x00000200, CS4BCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
34 __raw_writel(0x00000200, CS5ABCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
38 __raw_writel(0x00000200, CS5BBCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
42 __raw_writel(0x00000200, CS6ABCR); /* no idle cycles, normal space, 8 bit data bus */ in board_init()
/openbmc/u-boot/board/phytec/pcl063/
H A Dspl.c64 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
65 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
67 .refsel = 1, /* Refresh cycles at 32KHz */
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Demif.c50 * of the number of cycles. If the calculated number of cycles based on the
/openbmc/u-boot/board/bachmann/ot1200/
H A Dot1200_spl.c83 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
84 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
85 .refsel = 1, /* Refresh cycles at 32KHz */
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dlitesom.c127 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
128 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
130 .refsel = 0, /* Refresh cycles at 64KHz */
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Demif.c73 * of the number of cycles. If the calculated number of cycles based on the

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