1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2701ed16eSLinus Walleij /* 3701ed16eSLinus Walleij * (C) Copyright 2011 4701ed16eSLinus Walleij * Linaro 5701ed16eSLinus Walleij * Linus Walleij <linus.walleij@linaro.org> 6701ed16eSLinus Walleij * Register definitions for the External Bus Interface (EBI) 7701ed16eSLinus Walleij * found in the ARM Integrator AP and CP reference designs 8701ed16eSLinus Walleij */ 9701ed16eSLinus Walleij 10701ed16eSLinus Walleij #ifndef __ARM_EBI_H 11701ed16eSLinus Walleij #define __ARM_EBI_H 12701ed16eSLinus Walleij 13701ed16eSLinus Walleij #define EBI_BASE 0x12000000 14701ed16eSLinus Walleij 15701ed16eSLinus Walleij #define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */ 16701ed16eSLinus Walleij #define EBI_CSR1_REG 0x04 /* CS1 = Flash */ 17701ed16eSLinus Walleij #define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */ 18701ed16eSLinus Walleij #define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */ 19701ed16eSLinus Walleij /* 20701ed16eSLinus Walleij * The four upper bits are the waitstates for each chip select 21701ed16eSLinus Walleij * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles 22701ed16eSLinus Walleij */ 23701ed16eSLinus Walleij #define EBI_CSR_WAIT_MASK 0xF0 24701ed16eSLinus Walleij /* Whether memory is synchronous or asynchronous */ 25701ed16eSLinus Walleij #define EBI_CSR_SYNC_MASK 0xF7 26701ed16eSLinus Walleij #define EBI_CSR_ASYNC 0x00 27701ed16eSLinus Walleij #define EBI_CSR_SYNC 0x08 28701ed16eSLinus Walleij /* Whether memory is write enabled or not */ 29701ed16eSLinus Walleij #define EBI_CSR_WREN_MASK 0xFB 30701ed16eSLinus Walleij #define EBI_CSR_WREN_DISABLE 0x00 31701ed16eSLinus Walleij #define EBI_CSR_WREN_ENABLE 0x04 32701ed16eSLinus Walleij /* Memory bit width for each chip select */ 33701ed16eSLinus Walleij #define EBI_CSR_MEMSIZE_MASK 0xFC 34701ed16eSLinus Walleij #define EBI_CSR_MEMSIZE_8BIT 0x00 35701ed16eSLinus Walleij #define EBI_CSR_MEMSIZE_16BIT 0x01 36701ed16eSLinus Walleij #define EBI_CSR_MEMSIZE_32BIT 0x02 37701ed16eSLinus Walleij 38701ed16eSLinus Walleij /* 39701ed16eSLinus Walleij * The lock register need to be written with 0xa05f before anything in the 40701ed16eSLinus Walleij * EBI can be changed. 41701ed16eSLinus Walleij */ 42701ed16eSLinus Walleij #define EBI_LOCK_REG 0x20 43701ed16eSLinus Walleij #define EBI_UNLOCK_MAGIC 0xA05F 44701ed16eSLinus Walleij 45701ed16eSLinus Walleij #endif 46