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/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Darm,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
28 - arm,cortex-a9-scu
29 - arm,cortex-a5-scu
[all …]
H A Darm,vexpress-juno.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
37 further subvariants are released of the core tile, even more fine-granular
45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
49 - const: arm,vexpress,v2p-ca9
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H A Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
[all …]
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca5s.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A5 MPCore (V2P-CA5s)
8 * HBI-0225B
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA5s";
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Darm,twd-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Watchdog
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-wdt
[all …]
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Darm,twd-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Timer
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
17 The TWD is usually attached to a GIC to deliver its two per-processor
23 - arm,cortex-a9-twd-timer
[all …]
H A Darm,global_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stuart Menefy <stuart.menefy@st.com>
13 Cortex-A9 are often associated with a per-core Global timer.
18 - enum:
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
34 - compatible
35 - reg
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/openbmc/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf500.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a5";
28 intc: interrupt-controller@40003000 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
[all …]
/openbmc/linux/arch/arm/mach-versatile/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
52 bool "Include support for Integrator/IM-PD1"
60 The IM-PD1 is an add-on logic module for the Integrator which
62 The IM-PD1 can be found on the Integrator/PP2 platform.
77 bool "Integrator/CM922T-XA10 core module"
83 bool "Integrator/CM926EJ-S core module"
107 bool "Integrator/CM1026EJ-S core module"
113 bool "Integrator/CM1136JF-S core module"
129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
[all …]
H A Dplatsmp-vexpress.c1 // SPDX-License-Identifier: GPL-2.0-only
27 * The best way to detect a multi-cluster configuration in vexpress_smp_init_ops()
40 cci_node = of_parse_phandle(cpu_node, "cci-control-port", 0); in vexpress_smp_init_ops()
57 { .compatible = "arm,cortex-a5-scu", },
58 { .compatible = "arm,cortex-a9-scu", },
72 * system-wide flags register. The boot monitor waits in vexpress_smp_dt_prepare_cpus()
H A Dplatsmp-realview.c1 // SPDX-License-Identifier: GPL-2.0-only
21 { .compatible = "arm,arm11mp-scu", },
22 { .compatible = "arm,cortex-a9-scu", },
23 { .compatible = "arm,cortex-a5-scu", },
28 { .compatible = "arm,core-module-integrator", },
29 { .compatible = "arm,realview-eb-syscon", },
30 { .compatible = "arm,realview-pb11mp-syscon", },
31 { .compatible = "arm,realview-pbx-syscon", },
94 CPU_METHOD_OF_DECLARE(realview_smp, "arm,realview-smp", &realview_dt_smp_ops);
/openbmc/linux/Documentation/arch/arm/
H A Dmicrochip.rst7 ------------
11 It is important to note that the Microchip (previously Atmel) ARM-based MPU
15 git branches/tags and email subject always contain this "at91" sub-string.
19 ---------
25 - at91rm9200
29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-1768-32-bit-ARM920T-Embedded-Microprocessor-…
32 - at91sam9260
36 …ttp://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6221-32-bit-ARM926EJ-S-Embedded-Microprocesso…
38 - at91sam9xe
42 …ttp://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-6254-32-bit-ARM926EJ-S-Embedded-Microprocesso…
[all …]
/openbmc/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7a/
H A Dtune-cortexa5.inc1 DEFAULTTUNE ?= "cortexa5thf-neon"
3 require conf/machine/include/arm/arch-armv7a.inc
5 TUNEVALID[cortexa5] = "Enable Cortex-A5 specific processor optimizations"
6 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexa5', ' -mcpu=cortex-a5', '', d)}"
10 AVAILTUNES += "cortexa5 cortexa5t cortexa5-neon cortexa5t-neon cortexa5-neon-vfpv4 cortexa5t-neon-v…
11 ARMPKGARCH:tune-cortexa5 = "cortexa5"
12 ARMPKGARCH:tune-cortexa5t = "cortexa5"
13 ARMPKGARCH:tune-cortexa5-neon = "cortexa5"
14 ARMPKGARCH:tune-cortexa5t-neon = "cortexa5"
15 ARMPKGARCH:tune-cortexa5-neon-vfpv4 = "cortexa5"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/freescale/
H A Dfsl,vf610-mscm-ir.txt1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
8 which comes with a Cortex-A5/Cortex-M4 combination).
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
23 mscm_ir: interrupt-controller@40001800 {
24 compatible = "fsl,vf610-mscm-ir";
27 interrupt-controller;
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
[all …]
/openbmc/qemu/hw/cpu/
H A Da9mpcore.c2 * Cortex-A9MPCore internal peripheral emulation.
16 #include "hw/qdev-properties.h"
18 #include "target/arm/cpu-qom.h"
26 qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); in a9mp_priv_set_irq()
33 memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); in a9mp_priv_initfn()
34 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); in a9mp_priv_initfn()
36 object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU); in a9mp_priv_initfn()
38 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); in a9mp_priv_initfn()
40 object_initialize_child(obj, "gtimer", &s->gtimer, TYPE_A9_GTIMER); in a9mp_priv_initfn()
42 object_initialize_child(obj, "mptimer", &s->mptimer, TYPE_ARM_MPTIMER); in a9mp_priv_initfn()
[all …]
/openbmc/qemu/tests/tcg/arm/system/
H A Dtest-armv6m-undef.S2 * Test ARMv6-M UNDEFINED 32-bit instructions
7 * or later. See the COPYING file in the top-level directory.
11 * Test that UNDEFINED 32-bit instructions fault as expected. This is an
12 * interesting test because ARMv6-M shares code with its more fully-featured
16 * The emulator must be invoked with -semihosting so that the test case can
19 * Failures can be debugged with -d in_asm,int,exec,cpu and the
20 * gdbstub (-S -s).
24 .cpu cortex-m0
46 .word 0 /* 4-10. Reserved */
54 .word 0 /* 16-47. External Interrupts */
[all …]
/openbmc/linux/drivers/irqchip/
H A Dirq-vf610-mscm-ir.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-2015 Toradex AG
9 * one of the two available CPU's on Vybrid VF6xx SoC's (Cortex-A5 or
10 * Cortex-M4). The router will be configured transparently on a IRQ
14 * CPU 0, CPU 1 or both. The routing is useful for dual-core
18 * o It is required to setup the interrupt router even on single-core
28 #include <dt-bindings/interrupt-controller/arm-gic.h>
55 data->saved_irsprc[i] = readw_relaxed(data->mscm_ir_base + MSCM_IRSPRC(i)); in vf610_mscm_ir_save()
63 writew_relaxed(data->saved_irsprc[i], data->mscm_ir_base + MSCM_IRSPRC(i)); in vf610_mscm_ir_restore()
88 irq_hw_number_t hwirq = data->hwirq; in vf610_mscm_ir_enable()
[all …]
/openbmc/linux/arch/arm/boot/dts/unisoc/
H A Drda8810pl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&intc>;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a5";
29 compatible = "mmio-sram";
31 #address-cells = <1>;
[all …]
/openbmc/u-boot/arch/arm/mach-at91/
H A DKconfig118 bool "Atmel AT91SAM9M10G45-EK board"
128 bool "Mini-box picosam9g45 board"
133 bool "Atmel AT91SAM9N12-EK board"
144 bool "Atmel AT91SAM9X5-EK board"
171 a 64Mbit QSPI flash, KSZ8081 Phy and a Mac-address EEPROM
172 24AA02E48. The SAMA5D2 SiP integrates the ARM Cortex-A5
173 processor-based SAMA5D2 MPU with up to 1 Gbit DDR2-SDRAM
184 bool "SAMA5D3X-EK board"
287 source "board/mini-box/picosam9g45/Kconfig"
298 default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dsmp_twd.c1 // SPDX-License-Identifier: GPL-2.0-only
97 disable_percpu_irq(clk->irq); in twd_timer_stop()
118 * frequency. The timer is local to a cpu, so cross-call to the in twd_rate_change()
123 (void *)&cnd->new_rate, 1); in twd_rate_change()
173 twd_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5); in twd_calibrate_rate()
185 evt->event_handler(evt); in twd_handler()
231 enable_percpu_irq(clk->irq, 0); in twd_timer_setup()
244 clk->name = "local_timer"; in twd_timer_setup()
245 clk->features = twd_features; in twd_timer_setup()
246 clk->rating = 350; in twd_timer_setup()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dsamsung,exynos4212-fimc-is.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,exynos4212-fimc-is.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos4212/4412 SoC Imaging Subsystem (FIMC-IS)
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 The FIMC-IS is a subsystem for processing image signal from an image sensor.
15 The Exynos4x12 SoC series FIMC-IS V1.5 comprises of a dedicated ARM Cortex-A5
22 - samsung,exynos4212-fimc-is
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dmisc_gen5.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
24 #include <dt-bindings/reset/altr,rst-mgr.h>
47 -1,
65 { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
77 { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
96 return -EINVAL; in socfpga_fpga_id()
105 return -EINVAL; in socfpga_fpga_id()
121 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); in print_cpuinfo()
134 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; in arch_misc_init()
[all …]

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