1 // SPDX-License-Identifier: GPL-2.0+
3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
24 #include <dt-bindings/reset/altr,rst-mgr.h>
47 		-1,
65 	{ 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
77 	{ 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
96 		return -EINVAL;  in socfpga_fpga_id()
105 		return -EINVAL;  in socfpga_fpga_id()
121 		SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));  in print_cpuinfo()
134 	const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;  in arch_misc_init()
144  * Convert all NIC-301 AMBA slaves from secure to non-secure
148 	writel(0x1, &nic301_regs->lwhps2fpgaregs);  in socfpga_nic301_slave_ns()
149 	writel(0x1, &nic301_regs->hps2fpgaregs);  in socfpga_nic301_slave_ns()
150 	writel(0x1, &nic301_regs->acp);  in socfpga_nic301_slave_ns()
151 	writel(0x1, &nic301_regs->rom);  in socfpga_nic301_slave_ns()
152 	writel(0x1, &nic301_regs->ocram);  in socfpga_nic301_slave_ns()
153 	writel(0x1, &nic301_regs->sdrdata);  in socfpga_nic301_slave_ns()
164 	 * U-Boot : configure private timer, global timer and cpu component  in socfpga_sdram_remap_zero()
167 	setbits_le32(&scu_regs->sacr, 0xfff);  in socfpga_sdram_remap_zero()
174 	writel(remap, &nic301_regs->remap);  in socfpga_sdram_remap_zero()
176 	writel(0x1, &pl310->pl310_addr_filter_start);  in socfpga_sdram_remap_zero()
192 	writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);  in arch_early_init_r()
195 		iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);  in arch_early_init_r()
226 	u32 val = readl(&sdr_ctrl->static_cfg) | applymask;  in socfpga_sdram_apply_static_cfg()
231 	 * SDRAM. Luckily for us, we can abuse i-cache here to help us  in socfpga_sdram_apply_static_cfg()
233 	 * that the code is in one full i-cache line by branching past  in socfpga_sdram_apply_static_cfg()
234 	 * it and back. Once it is in the i-cache, we execute the core  in socfpga_sdram_apply_static_cfg()
237 	 * The code below uses 7 instructions, while the Cortex-A9 has  in socfpga_sdram_apply_static_cfg()
238 	 * 32-byte cachelines, thus the limit is 8 instructions total.  in socfpga_sdram_apply_static_cfg()
249 	: : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");  in socfpga_sdram_apply_static_cfg()
255 		writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);  in do_bridge_reset()
257 		writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);  in do_bridge_reset()
258 		writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);  in do_bridge_reset()
259 		writel(iswgrp_handoff[1], &nic301_regs->remap);  in do_bridge_reset()
261 		writel(0, &sysmgr_regs->fpgaintfgrp_module);  in do_bridge_reset()
262 		writel(0, &sdr_ctrl->fpgaport_rst);  in do_bridge_reset()
264 		writel(0, &reset_manager_base->brg_mod_reset);  in do_bridge_reset()
265 		writel(1, &nic301_regs->remap);  in do_bridge_reset()