14a073175SStefan AgnerFreescale Vybrid Miscellaneous System Control - Interrupt Router 24a073175SStefan Agner 34a073175SStefan AgnerThe MSCM IP contains multiple sub modules, this binding describes the second 44a073175SStefan Agnerblock of registers which control the interrupt router. The interrupt router 54a073175SStefan Agnerallows to configure the recipient of each peripheral interrupt. Furthermore 64a073175SStefan Agnerit controls the directed processor interrupts. The module is available in all 74a073175SStefan AgnerVybrid SoC's but is only really useful in dual core configurations (VF6xx 84a073175SStefan Agnerwhich comes with a Cortex-A5/Cortex-M4 combination). 94a073175SStefan Agner 104a073175SStefan AgnerRequired properties: 114a073175SStefan Agner- compatible: "fsl,vf610-mscm-ir" 124a073175SStefan Agner- reg: the register range of the MSCM Interrupt Router 134a073175SStefan Agner- fsl,cpucfg: The handle to the MSCM CPU configuration node, required 144a073175SStefan Agner to get the current CPU ID 154a073175SStefan Agner- interrupt-controller: Identifies the node as an interrupt controller 164a073175SStefan Agner- #interrupt-cells: Two cells, interrupt number and cells. 174a073175SStefan Agner The hardware interrupt number according to interrupt 184a073175SStefan Agner assignment of the interrupt router is required. 194a073175SStefan Agner Flags get passed only when using GIC as parent. Flags 204a073175SStefan Agner encoding as documented by the GIC bindings. 214a073175SStefan Agner 224a073175SStefan AgnerExample: 234a073175SStefan Agner mscm_ir: interrupt-controller@40001800 { 244a073175SStefan Agner compatible = "fsl,vf610-mscm-ir"; 254a073175SStefan Agner reg = <0x40001800 0x400>; 264a073175SStefan Agner fsl,cpucfg = <&mscm_cpucfg>; 274a073175SStefan Agner interrupt-controller; 284a073175SStefan Agner #interrupt-cells = <2>; 294a073175SStefan Agner interrupt-parent = <&intc>; 304a073175SStefan Agner } 31