183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2d1c559afSLey Foon Tan /*
3d1c559afSLey Foon Tan * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
4d1c559afSLey Foon Tan */
5d1c559afSLey Foon Tan
6d1c559afSLey Foon Tan #include <common.h>
7d1c559afSLey Foon Tan #include <asm/io.h>
8d1c559afSLey Foon Tan #include <errno.h>
9d1c559afSLey Foon Tan #include <fdtdec.h>
10b08c8c48SMasahiro Yamada #include <linux/libfdt.h>
11d1c559afSLey Foon Tan #include <altera.h>
12d1c559afSLey Foon Tan #include <miiphy.h>
13d1c559afSLey Foon Tan #include <netdev.h>
14d1c559afSLey Foon Tan #include <watchdog.h>
15d1c559afSLey Foon Tan #include <asm/arch/misc.h>
16d1c559afSLey Foon Tan #include <asm/arch/reset_manager.h>
17d1c559afSLey Foon Tan #include <asm/arch/scan_manager.h>
18d1c559afSLey Foon Tan #include <asm/arch/sdram.h>
19d1c559afSLey Foon Tan #include <asm/arch/system_manager.h>
20d1c559afSLey Foon Tan #include <asm/arch/nic301.h>
21d1c559afSLey Foon Tan #include <asm/arch/scu.h>
22d1c559afSLey Foon Tan #include <asm/pl310.h>
23d1c559afSLey Foon Tan
24d1c559afSLey Foon Tan #include <dt-bindings/reset/altr,rst-mgr.h>
25d1c559afSLey Foon Tan
26d1c559afSLey Foon Tan DECLARE_GLOBAL_DATA_PTR;
27d1c559afSLey Foon Tan
28d1c559afSLey Foon Tan static struct pl310_regs *const pl310 =
29d1c559afSLey Foon Tan (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
30d1c559afSLey Foon Tan static struct socfpga_system_manager *sysmgr_regs =
31d1c559afSLey Foon Tan (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
32d1c559afSLey Foon Tan static struct nic301_registers *nic301_regs =
33d1c559afSLey Foon Tan (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
34d1c559afSLey Foon Tan static struct scu_registers *scu_regs =
35d1c559afSLey Foon Tan (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
36d1c559afSLey Foon Tan
37d1c559afSLey Foon Tan /*
38877ec6ebSAng, Chee Hong * FPGA programming support for SoC FPGA Cyclone V
39877ec6ebSAng, Chee Hong */
40877ec6ebSAng, Chee Hong static Altera_desc altera_fpga[] = {
41877ec6ebSAng, Chee Hong {
42877ec6ebSAng, Chee Hong /* Family */
43877ec6ebSAng, Chee Hong Altera_SoCFPGA,
44877ec6ebSAng, Chee Hong /* Interface type */
45877ec6ebSAng, Chee Hong fast_passive_parallel,
46877ec6ebSAng, Chee Hong /* No limitation as additional data will be ignored */
47877ec6ebSAng, Chee Hong -1,
48877ec6ebSAng, Chee Hong /* No device function table */
49877ec6ebSAng, Chee Hong NULL,
50877ec6ebSAng, Chee Hong /* Base interface address specified in driver */
51877ec6ebSAng, Chee Hong NULL,
52877ec6ebSAng, Chee Hong /* No cookie implementation */
53877ec6ebSAng, Chee Hong 0
54877ec6ebSAng, Chee Hong },
55877ec6ebSAng, Chee Hong };
56877ec6ebSAng, Chee Hong
57d1c559afSLey Foon Tan static const struct {
58d1c559afSLey Foon Tan const u16 pn;
59d1c559afSLey Foon Tan const char *name;
60d1c559afSLey Foon Tan const char *var;
615e8c39d4SMasahiro Yamada } socfpga_fpga_model[] = {
62d1c559afSLey Foon Tan /* Cyclone V E */
63d1c559afSLey Foon Tan { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
64d1c559afSLey Foon Tan { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
65d1c559afSLey Foon Tan { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
66d1c559afSLey Foon Tan { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
67d1c559afSLey Foon Tan { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
68d1c559afSLey Foon Tan /* Cyclone V GX/GT */
69d1c559afSLey Foon Tan { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
70d1c559afSLey Foon Tan { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
71d1c559afSLey Foon Tan { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
72d1c559afSLey Foon Tan { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
73d1c559afSLey Foon Tan { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
74d1c559afSLey Foon Tan /* Cyclone V SE/SX/ST */
75d1c559afSLey Foon Tan { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
76d1c559afSLey Foon Tan { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
77d1c559afSLey Foon Tan { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
78d1c559afSLey Foon Tan { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
79d1c559afSLey Foon Tan /* Arria V */
80d1c559afSLey Foon Tan { 0x2d03, "Arria V, D5", "av_d5" },
81d1c559afSLey Foon Tan };
82d1c559afSLey Foon Tan
socfpga_fpga_id(const bool print_id)83d1c559afSLey Foon Tan static int socfpga_fpga_id(const bool print_id)
84d1c559afSLey Foon Tan {
85d1c559afSLey Foon Tan const u32 altera_mi = 0x6e;
86d1c559afSLey Foon Tan const u32 id = scan_mgr_get_fpga_id();
87d1c559afSLey Foon Tan
88d1c559afSLey Foon Tan const u32 lsb = id & 0x00000001;
89d1c559afSLey Foon Tan const u32 mi = (id >> 1) & 0x000007ff;
90d1c559afSLey Foon Tan const u32 pn = (id >> 12) & 0x0000ffff;
91d1c559afSLey Foon Tan const u32 version = (id >> 28) & 0x0000000f;
92d1c559afSLey Foon Tan int i;
93d1c559afSLey Foon Tan
94d1c559afSLey Foon Tan if ((mi != altera_mi) || (lsb != 1)) {
95d1c559afSLey Foon Tan printf("FPGA: Not Altera chip ID\n");
96d1c559afSLey Foon Tan return -EINVAL;
97d1c559afSLey Foon Tan }
98d1c559afSLey Foon Tan
99d1c559afSLey Foon Tan for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
100d1c559afSLey Foon Tan if (pn == socfpga_fpga_model[i].pn)
101d1c559afSLey Foon Tan break;
102d1c559afSLey Foon Tan
103d1c559afSLey Foon Tan if (i == ARRAY_SIZE(socfpga_fpga_model)) {
104d1c559afSLey Foon Tan printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id);
105d1c559afSLey Foon Tan return -EINVAL;
106d1c559afSLey Foon Tan }
107d1c559afSLey Foon Tan
108d1c559afSLey Foon Tan if (print_id)
109d1c559afSLey Foon Tan printf("FPGA: Altera %s, version 0x%01x\n",
110d1c559afSLey Foon Tan socfpga_fpga_model[i].name, version);
111d1c559afSLey Foon Tan return i;
112d1c559afSLey Foon Tan }
113d1c559afSLey Foon Tan
114d1c559afSLey Foon Tan /*
115d1c559afSLey Foon Tan * Print CPU information
116d1c559afSLey Foon Tan */
117d1c559afSLey Foon Tan #if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo(void)118d1c559afSLey Foon Tan int print_cpuinfo(void)
119d1c559afSLey Foon Tan {
120d1c559afSLey Foon Tan const u32 bsel =
121d1c559afSLey Foon Tan SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
122d1c559afSLey Foon Tan
123d1c559afSLey Foon Tan puts("CPU: Altera SoCFPGA Platform\n");
124d1c559afSLey Foon Tan socfpga_fpga_id(1);
125d1c559afSLey Foon Tan
126d1c559afSLey Foon Tan printf("BOOT: %s\n", bsel_str[bsel].name);
127d1c559afSLey Foon Tan return 0;
128d1c559afSLey Foon Tan }
129d1c559afSLey Foon Tan #endif
130d1c559afSLey Foon Tan
131d1c559afSLey Foon Tan #ifdef CONFIG_ARCH_MISC_INIT
arch_misc_init(void)132d1c559afSLey Foon Tan int arch_misc_init(void)
133d1c559afSLey Foon Tan {
134d1c559afSLey Foon Tan const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
135d1c559afSLey Foon Tan const int fpga_id = socfpga_fpga_id(0);
136382bee57SSimon Glass env_set("bootmode", bsel_str[bsel].mode);
137d1c559afSLey Foon Tan if (fpga_id >= 0)
138382bee57SSimon Glass env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
139*473f5567SSimon Goldschmidt return 0;
140d1c559afSLey Foon Tan }
141d1c559afSLey Foon Tan #endif
142d1c559afSLey Foon Tan
143d1c559afSLey Foon Tan /*
144d1c559afSLey Foon Tan * Convert all NIC-301 AMBA slaves from secure to non-secure
145d1c559afSLey Foon Tan */
socfpga_nic301_slave_ns(void)146d1c559afSLey Foon Tan static void socfpga_nic301_slave_ns(void)
147d1c559afSLey Foon Tan {
148d1c559afSLey Foon Tan writel(0x1, &nic301_regs->lwhps2fpgaregs);
149d1c559afSLey Foon Tan writel(0x1, &nic301_regs->hps2fpgaregs);
150d1c559afSLey Foon Tan writel(0x1, &nic301_regs->acp);
151d1c559afSLey Foon Tan writel(0x1, &nic301_regs->rom);
152d1c559afSLey Foon Tan writel(0x1, &nic301_regs->ocram);
153d1c559afSLey Foon Tan writel(0x1, &nic301_regs->sdrdata);
154d1c559afSLey Foon Tan }
155d1c559afSLey Foon Tan
socfpga_sdram_remap_zero(void)156e4ff8420SSimon Goldschmidt void socfpga_sdram_remap_zero(void)
157e4ff8420SSimon Goldschmidt {
15830bade20SSimon Goldschmidt u32 remap;
15930bade20SSimon Goldschmidt
160e4ff8420SSimon Goldschmidt socfpga_nic301_slave_ns();
161e4ff8420SSimon Goldschmidt
162e4ff8420SSimon Goldschmidt /*
163e4ff8420SSimon Goldschmidt * Private components security:
164e4ff8420SSimon Goldschmidt * U-Boot : configure private timer, global timer and cpu component
165e4ff8420SSimon Goldschmidt * access as non secure for kernel stage (as required by Linux)
166e4ff8420SSimon Goldschmidt */
167e4ff8420SSimon Goldschmidt setbits_le32(&scu_regs->sacr, 0xfff);
168e4ff8420SSimon Goldschmidt
169e4ff8420SSimon Goldschmidt /* Configure the L2 controller to make SDRAM start at 0 */
17030bade20SSimon Goldschmidt remap = 0x1; /* remap.mpuzero */
17130bade20SSimon Goldschmidt /* Keep fpga bridge enabled when running from FPGA onchip RAM */
17230bade20SSimon Goldschmidt if (socfpga_is_booting_from_fpga())
17330bade20SSimon Goldschmidt remap |= 0x8; /* remap.hps2fpga */
17430bade20SSimon Goldschmidt writel(remap, &nic301_regs->remap);
17530bade20SSimon Goldschmidt
176e4ff8420SSimon Goldschmidt writel(0x1, &pl310->pl310_addr_filter_start);
177e4ff8420SSimon Goldschmidt }
178e4ff8420SSimon Goldschmidt
179d1c559afSLey Foon Tan static u32 iswgrp_handoff[8];
180d1c559afSLey Foon Tan
arch_early_init_r(void)181d1c559afSLey Foon Tan int arch_early_init_r(void)
182d1c559afSLey Foon Tan {
183d1c559afSLey Foon Tan int i;
184d1c559afSLey Foon Tan
185d1c559afSLey Foon Tan /*
186d1c559afSLey Foon Tan * Write magic value into magic register to unlock support for
187d1c559afSLey Foon Tan * issuing warm reset. The ancient kernel code expects this
188d1c559afSLey Foon Tan * value to be written into the register by the bootloader, so
189d1c559afSLey Foon Tan * to support that old code, we write it here instead of in the
190d1c559afSLey Foon Tan * reset_cpu() function just before resetting the CPU.
191d1c559afSLey Foon Tan */
192d1c559afSLey Foon Tan writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
193d1c559afSLey Foon Tan
194d1c559afSLey Foon Tan for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
195d1c559afSLey Foon Tan iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
196d1c559afSLey Foon Tan
197d1c559afSLey Foon Tan socfpga_bridges_reset(1);
198d1c559afSLey Foon Tan
199e4ff8420SSimon Goldschmidt socfpga_sdram_remap_zero();
200d1c559afSLey Foon Tan
201d1c559afSLey Foon Tan /* Add device descriptor to FPGA device table */
202877ec6ebSAng, Chee Hong socfpga_fpga_add(&altera_fpga[0]);
203d1c559afSLey Foon Tan
204d1c559afSLey Foon Tan #ifdef CONFIG_DESIGNWARE_SPI
205d1c559afSLey Foon Tan /* Get Designware SPI controller out of reset */
206d1c559afSLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
207d1c559afSLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
208d1c559afSLey Foon Tan #endif
209d1c559afSLey Foon Tan
210d1c559afSLey Foon Tan #ifdef CONFIG_NAND_DENALI
211d1c559afSLey Foon Tan socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
212d1c559afSLey Foon Tan #endif
213d1c559afSLey Foon Tan
214d1c559afSLey Foon Tan return 0;
215d1c559afSLey Foon Tan }
216d1c559afSLey Foon Tan
217b4b9814fSTom Rini #ifndef CONFIG_SPL_BUILD
218b4b9814fSTom Rini static struct socfpga_reset_manager *reset_manager_base =
219b4b9814fSTom Rini (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
220b4b9814fSTom Rini static struct socfpga_sdr_ctrl *sdr_ctrl =
221b4b9814fSTom Rini (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
222b4b9814fSTom Rini
socfpga_sdram_apply_static_cfg(void)223d1c559afSLey Foon Tan static void socfpga_sdram_apply_static_cfg(void)
224d1c559afSLey Foon Tan {
225d1c559afSLey Foon Tan const u32 applymask = 0x8;
226d1c559afSLey Foon Tan u32 val = readl(&sdr_ctrl->static_cfg) | applymask;
227d1c559afSLey Foon Tan
228d1c559afSLey Foon Tan /*
229d1c559afSLey Foon Tan * SDRAM staticcfg register specific:
230d1c559afSLey Foon Tan * When applying the register setting, the CPU must not access
231d1c559afSLey Foon Tan * SDRAM. Luckily for us, we can abuse i-cache here to help us
232d1c559afSLey Foon Tan * circumvent the SDRAM access issue. The idea is to make sure
233d1c559afSLey Foon Tan * that the code is in one full i-cache line by branching past
234d1c559afSLey Foon Tan * it and back. Once it is in the i-cache, we execute the core
235d1c559afSLey Foon Tan * of the code and apply the register settings.
236d1c559afSLey Foon Tan *
237d1c559afSLey Foon Tan * The code below uses 7 instructions, while the Cortex-A9 has
238d1c559afSLey Foon Tan * 32-byte cachelines, thus the limit is 8 instructions total.
239d1c559afSLey Foon Tan */
240d1c559afSLey Foon Tan asm volatile(
241d1c559afSLey Foon Tan ".align 5 \n"
242d1c559afSLey Foon Tan " b 2f \n"
243d1c559afSLey Foon Tan "1: str %0, [%1] \n"
244d1c559afSLey Foon Tan " dsb \n"
245d1c559afSLey Foon Tan " isb \n"
246d1c559afSLey Foon Tan " b 3f \n"
247d1c559afSLey Foon Tan "2: b 1b \n"
248d1c559afSLey Foon Tan "3: nop \n"
249d1c559afSLey Foon Tan : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
250d1c559afSLey Foon Tan }
251d1c559afSLey Foon Tan
do_bridge_reset(int enable)25210f9e4b1SLey Foon Tan void do_bridge_reset(int enable)
253d1c559afSLey Foon Tan {
25410f9e4b1SLey Foon Tan if (enable) {
255d1c559afSLey Foon Tan writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
256d1c559afSLey Foon Tan socfpga_sdram_apply_static_cfg();
257d1c559afSLey Foon Tan writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
258d1c559afSLey Foon Tan writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
259d1c559afSLey Foon Tan writel(iswgrp_handoff[1], &nic301_regs->remap);
26010f9e4b1SLey Foon Tan } else {
261d1c559afSLey Foon Tan writel(0, &sysmgr_regs->fpgaintfgrp_module);
262d1c559afSLey Foon Tan writel(0, &sdr_ctrl->fpgaport_rst);
263d1c559afSLey Foon Tan socfpga_sdram_apply_static_cfg();
264d1c559afSLey Foon Tan writel(0, &reset_manager_base->brg_mod_reset);
265d1c559afSLey Foon Tan writel(1, &nic301_regs->remap);
266d1c559afSLey Foon Tan }
267d1c559afSLey Foon Tan }
268b4b9814fSTom Rini #endif
269