| /openbmc/u-boot/board/freescale/mpc8572ds/ |
| H A D | README | 98 1. Build kernel image for core0:
107 d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
128 3. Create dtb for core0:
157 c. Bring up core0's kernel(on the same U-Boot console):
160 => tftp 1000000 8572/uImage.core0
165 Please note only core0 will run U-Boot, core1 starts kernel directly after
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| /openbmc/linux/drivers/remoteproc/ |
| H A D | ti_k3_r5_remoteproc.c | 439 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to
442 * private to each core. Only Core0 needs to be unhalted for running the
509 * both cores, but with only Core0 unhalted. This function re-uses the same
538 * mode requires the boot vector to be configured only for Core0, and then
540 * first followed by Core0. The Split-mode requires that Core0 to be maintained
542 * always only after Core0 is started).
544 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute
545 * code, so only Core0 needs to be unhalted. The function uses the same logic
554 struct k3_r5_core *core0, *core; in k3_r5_rproc_start() local
577 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, in k3_r5_rproc_start()
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| /openbmc/linux/arch/powerpc/boot/dts/fsl/ |
| H A D | p1020rdb-pc_camp_core0.dts | 3 * P1020 RDB-PC Core0 Device Tree Source in CAMP mode.
7 * This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
10 * Please note to add "-b 0" for core0's dts compiling.
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| H A D | mpc8572ds_camp_core0.dts | 3 * MPC8572 DS Core0 Device Tree Source in CAMP mode.
7 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
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| /openbmc/linux/Documentation/devicetree/bindings/gpu/ |
| H A D | brcm,bcm-v3d.yaml | 26 - description: core0 register (required)
34 - const: core0
70 reg-names = "hub", "core0", "bridge", "gca";
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| H A D | arm,mali-bifrost.yaml | 183 - const: core0
206 - const: core0
224 - const: core0
240 - const: core0
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| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | qcom,sdm845-venus-v2.yaml | 55 video-core0:
83 - video-core0
115 video-core0 {
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| H A D | qcom,sdm845-venus.yaml | 38 video-core0:
93 - video-core0
116 video-core0 {
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| /openbmc/linux/arch/arm/boot/dts/intel/axm/ |
| H A D | axm5516-cpus.dtsi | 15 core0 {
29 core0 {
43 core0 {
57 core0 {
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| /openbmc/linux/sound/soc/sof/intel/ |
| H A D | lnl.h | 12 #define LNL_DSP_REG_HFDSC 0x160200 /* DSP core0 status */
13 #define LNL_DSP_REG_HFDEC 0x160204 /* DSP core0 error */
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| H A D | mtl.h | 79 #define MTL_DSP_REG_HFFLGPXQWY 0x163200 /* DSP core0 status */
80 #define MTL_DSP_REG_HFFLGPXQWY_ERROR 0x163204 /* DSP core0 error */
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| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.core_prefetch | 9 Mask[0] = core0
16 core0 prefetch should not be disabled i.e. Mask[0] should never be set.
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| /openbmc/linux/arch/arm64/boot/dts/amd/ |
| H A D | amd-seattle-cpus.dtsi | 10 core0 {
18 core0 {
26 core0 {
34 core0 {
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| /openbmc/phosphor-dbus-interfaces/yaml/com/ibm/ipzvpd/ |
| H A D | LWP0.interface.yaml | 15 The "20" keyword.Core0 L2 Line delete.
31 The "30" keyword.Core0 L2 Line delete.
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| H A D | LWP2.interface.yaml | 15 The "20" keyword.Core0 L2 Line delete.
31 The "30" keyword.Core0 L2 Line delete.
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| H A D | LWP5.interface.yaml | 15 The "20" keyword.Core0 L2 Line delete.
31 The "30" keyword.Core0 L2 Line delete.
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| H A D | LWP1.interface.yaml | 15 The "20" keyword.Core0 L2 Line delete.
31 The "30" keyword.Core0 L2 Line delete.
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| H A D | LWP6.interface.yaml | 15 The "20" keyword.Core0 L2 Line delete.
31 The "30" keyword.Core0 L2 Line delete.
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| H A D | LWP7.interface.yaml | 15 The "20" keyword.Core0 L2 Line delete.
31 The "30" keyword.Core0 L2 Line delete.
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| H A D | LWP3.interface.yaml | 15 The "20" keyword.Core0 L2 Line delete.
31 The "30" keyword.Core0 L2 Line delete.
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| H A D | LWP4.interface.yaml | 15 The "20" keyword.Core0 L2 Line delete.
31 The "30" keyword.Core0 L2 Line delete.
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| /openbmc/linux/Documentation/devicetree/bindings/cpu/ |
| H A D | cpu-topology.txt | 194 core0 {
214 core0 {
236 core0 {
255 core0 {
413 core0 {
428 core0 {
507 core0 {
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| /openbmc/linux/arch/arm64/boot/dts/hisilicon/ |
| H A D | hip05.dtsi | 27 core0 {
41 core0 {
55 core0 {
69 core0 {
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | meson-gxm.dtsi | 15 core0 {
30 core0 {
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| /openbmc/u-boot/include/configs/ |
| H A D | p1_p2_rdb_pc.h | 49 * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
50 * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
51 * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
52 * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
53 * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
54 * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
55 * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
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