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Revision tags: v6.6.35, v6.6.34, v6.6.33, v6.6.32, v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
8aeb3dc8 |
| 03-Apr-2024 |
Peter Ujfalusi <peter.ujfalusi@linux.intel.com> |
ASoC: SOF: Intel: mtl: Correct rom_status_reg
[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]
ACE1 architecture changed the place where the ROM updates the status code
from the shared
ASoC: SOF: Intel: mtl: Correct rom_status_reg
[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]
ACE1 architecture changed the place where the ROM updates the status code
from the shared SRAM window to HFFLGP1QW0 register for the status and
HFFLGP1QW0 + 4 for the error code.
The rom_status_reg is not used on MTL because it was wrongly assigned based
on older platform convention (SRAM window) and it was giving inconsistent
readings.
Fixes: 064520e8aeaa ("ASoC: SOF: Intel: Add support for MeteorLake (MTL)")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>
Link: https://msgid.link/r/20240403105210.17949-3-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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|
Revision tags: v6.6.35, v6.6.34, v6.6.33, v6.6.32, v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
8aeb3dc8 |
| 03-Apr-2024 |
Peter Ujfalusi <peter.ujfalusi@linux.intel.com> |
ASoC: SOF: Intel: mtl: Correct rom_status_reg
[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]
ACE1 architecture changed the place where the ROM updates the status code
from the shared
ASoC: SOF: Intel: mtl: Correct rom_status_reg
[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]
ACE1 architecture changed the place where the ROM updates the status code
from the shared SRAM window to HFFLGP1QW0 register for the status and
HFFLGP1QW0 + 4 for the error code.
The rom_status_reg is not used on MTL because it was wrongly assigned based
on older platform convention (SRAM window) and it was giving inconsistent
readings.
Fixes: 064520e8aeaa ("ASoC: SOF: Intel: Add support for MeteorLake (MTL)")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>
Link: https://msgid.link/r/20240403105210.17949-3-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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|
Revision tags: v6.6.35, v6.6.34, v6.6.33, v6.6.32, v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
8aeb3dc8 |
| 03-Apr-2024 |
Peter Ujfalusi <peter.ujfalusi@linux.intel.com> |
ASoC: SOF: Intel: mtl: Correct rom_status_reg
[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]
ACE1 architecture changed the place where the ROM updates the status code
from the shared
ASoC: SOF: Intel: mtl: Correct rom_status_reg
[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]
ACE1 architecture changed the place where the ROM updates the status code
from the shared SRAM window to HFFLGP1QW0 register for the status and
HFFLGP1QW0 + 4 for the error code.
The rom_status_reg is not used on MTL because it was wrongly assigned based
on older platform convention (SRAM window) and it was giving inconsistent
readings.
Fixes: 064520e8aeaa ("ASoC: SOF: Intel: Add support for MeteorLake (MTL)")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>
Link: https://msgid.link/r/20240403105210.17949-3-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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|
Revision tags: v6.6.35, v6.6.34, v6.6.33, v6.6.32, v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
8aeb3dc8 |
| 03-Apr-2024 |
Peter Ujfalusi <peter.ujfalusi@linux.intel.com> |
ASoC: SOF: Intel: mtl: Correct rom_status_reg
[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]
ACE1 architecture changed the place where the ROM updates the status code
from the shared
ASoC: SOF: Intel: mtl: Correct rom_status_reg
[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]
ACE1 architecture changed the place where the ROM updates the status code
from the shared SRAM window to HFFLGP1QW0 register for the status and
HFFLGP1QW0 + 4 for the error code.
The rom_status_reg is not used on MTL because it was wrongly assigned based
on older platform convention (SRAM window) and it was giving inconsistent
readings.
Fixes: 064520e8aeaa ("ASoC: SOF: Intel: Add support for MeteorLake (MTL)")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>
Link: https://msgid.link/r/20240403105210.17949-3-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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|
Revision tags: v6.6.35, v6.6.34, v6.6.33, v6.6.32, v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
8aeb3dc8 |
| 03-Apr-2024 |
Peter Ujfalusi <peter.ujfalusi@linux.intel.com> |
ASoC: SOF: Intel: mtl: Correct rom_status_reg
[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]
ACE1 architecture changed the place where the ROM updates the status code
from the shared
ASoC: SOF: Intel: mtl: Correct rom_status_reg
[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]
ACE1 architecture changed the place where the ROM updates the status code
from the shared SRAM window to HFFLGP1QW0 register for the status and
HFFLGP1QW0 + 4 for the error code.
The rom_status_reg is not used on MTL because it was wrongly assigned based
on older platform convention (SRAM window) and it was giving inconsistent
readings.
Fixes: 064520e8aeaa ("ASoC: SOF: Intel: Add support for MeteorLake (MTL)")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>
Link: https://msgid.link/r/20240403105210.17949-3-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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|
Revision tags: v6.6.35, v6.6.34, v6.6.33, v6.6.32, v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
8aeb3dc8 |
| 03-Apr-2024 |
Peter Ujfalusi <peter.ujfalusi@linux.intel.com> |
ASoC: SOF: Intel: mtl: Correct rom_status_reg
[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]
ACE1 architecture changed the place where the ROM updates the status code
from the shared
ASoC: SOF: Intel: mtl: Correct rom_status_reg
[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]
ACE1 architecture changed the place where the ROM updates the status code
from the shared SRAM window to HFFLGP1QW0 register for the status and
HFFLGP1QW0 + 4 for the error code.
The rom_status_reg is not used on MTL because it was wrongly assigned based
on older platform convention (SRAM window) and it was giving inconsistent
readings.
Fixes: 064520e8aeaa ("ASoC: SOF: Intel: Add support for MeteorLake (MTL)")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>
Link: https://msgid.link/r/20240403105210.17949-3-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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|
Revision tags: v6.6.35, v6.6.34, v6.6.33, v6.6.32, v6.6.31, v6.6.30, v6.6.29, v6.6.28, v6.6.27, v6.6.26, v6.6.25, v6.6.24 |
|
| #
8aeb3dc8 |
| 03-Apr-2024 |
Peter Ujfalusi <peter.ujfalusi@linux.intel.com> |
ASoC: SOF: Intel: mtl: Correct rom_status_reg
[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]
ACE1 architecture changed the place where the ROM updates the status code
from the shared
ASoC: SOF: Intel: mtl: Correct rom_status_reg
[ Upstream commit 1f1b820dc3c65b6883da3130ba3b8624dcbf87db ]
ACE1 architecture changed the place where the ROM updates the status code
from the shared SRAM window to HFFLGP1QW0 register for the status and
HFFLGP1QW0 + 4 for the error code.
The rom_status_reg is not used on MTL because it was wrongly assigned based
on older platform convention (SRAM window) and it was giving inconsistent
readings.
Fixes: 064520e8aeaa ("ASoC: SOF: Intel: Add support for MeteorLake (MTL)")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@intel.com>
Link: https://msgid.link/r/20240403105210.17949-3-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
show more ...
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|
Revision tags: v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4 |
|
| #
e0f96246 |
| 15-Sep-2023 |
Ranjani Sridharan <ranjani.sridharan@linux.intel.com> |
ASoC: SOF: Intel: MTL: Reduce the DSP init timeout
20s seems unnecessarily large for the DSP init timeout. This coupled with
multiple FW boot attempts causes an excessive delay in the error path whe
ASoC: SOF: Intel: MTL: Reduce the DSP init timeout
20s seems unnecessarily large for the DSP init timeout. This coupled with
multiple FW boot attempts causes an excessive delay in the error path when
booting in recovery mode. Reduce it to 0.5s and use the existing
HDA_DSP_INIT_TIMEOUT_US.
Link: https://github.com/thesofproject/linux/issues/4565
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20230915134153.9688-1-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
show more ...
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|
Revision tags: v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44 |
|
| #
c22d5327 |
| 07-Aug-2023 |
Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> |
ASoC: SOF: Intel: split MTL and LNL operations
It was just a matter of time before we found a case where we needed
separate ops for MTL and LNL. For LNL we need to set the DMIC/SSP
OFLEN bit in the
ASoC: SOF: Intel: split MTL and LNL operations
It was just a matter of time before we found a case where we needed
separate ops for MTL and LNL. For LNL we need to set the DMIC/SSP
OFLEN bit in the probe and resume steps, and this can only be done
cleanly with separate ops.
The function prototypes in mtl.h were added in the same order as their
implementation in mtl.c.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20230807210959.506849-8-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
show more ...
|
|
Revision tags: v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32 |
|
| #
730025cf |
| 02-Jun-2023 |
Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> |
ASoC: SOF: Intel: mtl: prepare for code reuse
Some functions can be used for newer LNL hardware.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Péter Ujfalu
ASoC: SOF: Intel: mtl: prepare for code reuse
Some functions can be used for newer LNL hardware.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20230602205620.310879-9-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
show more ...
|
|
Revision tags: v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17 |
|
| #
75034eb5 |
| 10-Mar-2023 |
Peter Ujfalusi <peter.ujfalusi@linux.intel.com> |
ASoC: SOF: Intel: MTL: Don't access EM2
This reverts commit 2b5a30cafb2ef ("ASoC: SOF: Intel: MTL: Enable
DMI L1").
It came to our attention that the access to the EM2 register is restricted
to the
ASoC: SOF: Intel: MTL: Don't access EM2
This reverts commit 2b5a30cafb2ef ("ASoC: SOF: Intel: MTL: Enable
DMI L1").
It came to our attention that the access to the EM2 register is restricted
to the DSP side on MTL compared to prior platforms.
Writing to it from the host side has no effect (negative or positive), it
is better to remove the code to not cause confusion and wrong impression.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20230310133454.15362-1-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
show more ...
|
|
Revision tags: v6.1.16, v6.1.15, v6.1.14, v6.1.13 |
|
| #
2b5a30ca |
| 20-Feb-2023 |
Ranjani Sridharan <ranjani.sridharan@linux.intel.com> |
ASoC: SOF: Intel: MTL: Enable DMI L1
DMI L1 should be enabled unconditionally after FW boot is complete.
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Rander Wan
ASoC: SOF: Intel: MTL: Enable DMI L1
DMI L1 should be enabled unconditionally after FW boot is complete.
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20230220075804.4829-4-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
show more ...
|
|
Revision tags: v6.2, v6.1.12, v6.1.11, v6.1.10 |
|
| #
faceb344 |
| 02-Feb-2023 |
Rander Wang <rander.wang@intel.com> |
ASoC: SOF: Intel: mtl: add get_stream_position support
Get HDaudio link position for current stream delay calculation
from hda registers.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Reviewed
ASoC: SOF: Intel: mtl: add get_stream_position support
Get HDaudio link position for current stream delay calculation
from hda registers.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20230202132954.26773-9-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
show more ...
|
|
Revision tags: v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78 |
|
| #
09e3c1d3 |
| 07-Nov-2022 |
Rander Wang <rander.wang@intel.com> |
ASoC: SOF: Intel: add d0i3 definition for MTL
MTL has a different offset of d0i3 compared to cavs platforms.
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Rander
ASoC: SOF: Intel: add d0i3 definition for MTL
MTL has a different offset of d0i3 compared to cavs platforms.
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Rander Wang <rander.wang@intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20221107164154.21925-2-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
show more ...
|
|
Revision tags: v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48 |
|
| #
064520e8 |
| 15-Jun-2022 |
Bard Liao <yung-chuan.liao@linux.intel.com> |
ASoC: SOF: Intel: Add support for MeteorLake (MTL)
Add platform abstraction for the Meteor Lake platform.
This platform has significant differences compared to the TGL/ADL
generation: it relies on
ASoC: SOF: Intel: Add support for MeteorLake (MTL)
Add platform abstraction for the Meteor Lake platform.
This platform has significant differences compared to the TGL/ADL
generation: it relies on new hardware using the code name 'ACE' and
only supports the INTEL_IPC4 protocol and firmware architecture based
on the Zephyr RTOS
Co-developed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Link: https://lore.kernel.org/r/20220615084348.3489-3-yung-chuan.liao@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
show more ...
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