439  * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to
442  * private to each core. Only Core0 needs to be unhalted for running the
509  * both cores, but with only Core0 unhalted. This function re-uses the same
538  * mode requires the boot vector to be configured only for Core0, and then
540  * first followed by Core0. The Split-mode requires that Core0 to be maintained
542  * always only after Core0 is started).
544  * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute
545  * code, so only Core0 needs to be unhalted. The function uses the same logic
554 	struct k3_r5_core *core0, *core;  in k3_r5_rproc_start()  local
577 		core0 = list_first_entry(&cluster->cores, struct k3_r5_core,  in k3_r5_rproc_start()
579 		if (core != core0 && core0->rproc->state == RPROC_OFFLINE) {  in k3_r5_rproc_start()
610  * performed first on Core0 followed by Core1. The Split-mode requires that
611  * Core0 to be maintained always in a higher power state that Core1 (implying
612  * Core1 needs to be stopped first before Core0).
614  * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute
615  * code, so only Core0 needs to be halted. The function uses the same logic
826  * and retrieved using Core0.
830  * They are identically configured in LockStep mode using the primary Core0
840 	struct k3_r5_core *core0, *core, *temp;  in k3_r5_rproc_configure()  local
848 	core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);  in k3_r5_rproc_configure()
852 		core = core0;  in k3_r5_rproc_configure()
882 	if (core == core0) {  in k3_r5_rproc_configure()
886 		 * on Core0 and system firmware will NACK any requests  in k3_r5_rproc_configure()
924 		 * and TEINIT config is only allowed with Core0.  in k3_r5_rproc_configure()
1064  * cores are usable in Split-mode, but only the Core0 TCMs can be used in
1069  * corresponding Core0 TCM. The SoC memory map uses the larger 64 KB sizes for
1070  * the Core0 TCMs, and the dts representation reflects this increased size on
1071  * supported SoCs. The Core0 TCM sizes therefore have to be adjusted to only
1079 	struct k3_r5_core *core0;  in k3_r5_adjust_tcm_sizes()  local
1087 	core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);  in k3_r5_adjust_tcm_sizes()
1088 	if (core == core0) {  in k3_r5_adjust_tcm_sizes()
1122 	struct k3_r5_core *core0;  in k3_r5_rproc_configure_mode()  local
1126 	core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);  in k3_r5_rproc_configure_mode()
1205 		if (core == core0)  in k3_r5_rproc_configure_mode()
1299 		 * R5 cores require to be powered on sequentially, core0  in k3_r5_cluster_rproc_init()
1306 		 * core0 due to thread execution order.  in k3_r5_cluster_rproc_init()
1339 	/* undo core0 upon any failures on core1 in split-mode */  in k3_r5_cluster_rproc_init()