1064520e8SBard Liao /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2064520e8SBard Liao /* 3064520e8SBard Liao * This file is provided under a dual BSD/GPLv2 license. When using or 4064520e8SBard Liao * redistributing this file, you may do so under either license. 5064520e8SBard Liao * 6064520e8SBard Liao * Copyright(c) 2020-2022 Intel Corporation. All rights reserved. 7064520e8SBard Liao */ 8064520e8SBard Liao 9faceb344SRander Wang /* HDA Registers */ 10faceb344SRander Wang #define MTL_PPLCLLPL_BASE 0x948 11faceb344SRander Wang #define MTL_PPLCLLPU_STRIDE 0x10 12faceb344SRander Wang #define MTL_PPLCLLPL(x) (MTL_PPLCLLPL_BASE + (x) * MTL_PPLCLLPU_STRIDE) 13faceb344SRander Wang #define MTL_PPLCLLPU(x) (MTL_PPLCLLPL_BASE + 0x4 + (x) * MTL_PPLCLLPU_STRIDE) 14faceb344SRander Wang 15064520e8SBard Liao /* DSP Registers */ 16064520e8SBard Liao #define MTL_HFDSSCS 0x1000 17064520e8SBard Liao #define MTL_HFDSSCS_SPA_MASK BIT(16) 18064520e8SBard Liao #define MTL_HFDSSCS_CPA_MASK BIT(24) 19064520e8SBard Liao #define MTL_HFSNDWIE 0x114C 20064520e8SBard Liao #define MTL_HFPWRCTL 0x1D18 21064520e8SBard Liao #define MTL_HfPWRCTL_WPIOXPG(x) BIT((x) + 8) 22064520e8SBard Liao #define MTL_HFPWRCTL_WPDSPHPXPG BIT(0) 23064520e8SBard Liao #define MTL_HFPWRSTS 0x1D1C 24064520e8SBard Liao #define MTL_HFPWRSTS_DSPHPXPGS_MASK BIT(0) 25064520e8SBard Liao #define MTL_HFINTIPPTR 0x1108 26064520e8SBard Liao #define MTL_IRQ_INTEN_L_HOST_IPC_MASK BIT(0) 27064520e8SBard Liao #define MTL_IRQ_INTEN_L_SOUNDWIRE_MASK BIT(6) 28064520e8SBard Liao #define MTL_HFINTIPPTR_PTR_MASK GENMASK(20, 0) 29064520e8SBard Liao 3009e3c1d3SRander Wang #define MTL_HDA_VS_D0I3C 0x1D4A 3109e3c1d3SRander Wang 32064520e8SBard Liao #define MTL_DSP2CXCAP_PRIMARY_CORE 0x178D00 33064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE 0x178D04 34064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK BIT(0) 35064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK BIT(8) 36064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL GENMASK(25, 24) 37064520e8SBard Liao #define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT 24 38064520e8SBard Liao 39064520e8SBard Liao /* IPC Registers */ 40064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDR 0x73200 41064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDR_BUSY BIT(31) 42064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDR_MSG_MASK GENMASK(30, 0) 43064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDA 0x73204 44064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDA_BUSY BIT(31) 45064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDR 0x73210 46064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDR_BUSY BIT(31) 47064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDR_MSG_MASK GENMASK(30, 0) 48064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDA 0x73214 49064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDA_DONE BIT(31) 50064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDA_MSG_MASK GENMASK(30, 0) 51064520e8SBard Liao #define MTL_DSP_REG_HFIPCXCTL 0x73228 52064520e8SBard Liao #define MTL_DSP_REG_HFIPCXCTL_BUSY BIT(0) 53064520e8SBard Liao #define MTL_DSP_REG_HFIPCXCTL_DONE BIT(1) 54064520e8SBard Liao #define MTL_DSP_REG_HFIPCXTDDY 0x73300 55064520e8SBard Liao #define MTL_DSP_REG_HFIPCXIDDY 0x73380 56064520e8SBard Liao #define MTL_DSP_REG_HfHIPCIE 0x1140 57064520e8SBard Liao #define MTL_DSP_REG_HfHIPCIE_IE_MASK BIT(0) 58064520e8SBard Liao #define MTL_DSP_REG_HfSNDWIE 0x114C 59064520e8SBard Liao #define MTL_DSP_REG_HfSNDWIE_IE_MASK GENMASK(3, 0) 60064520e8SBard Liao 61064520e8SBard Liao #define MTL_DSP_IRQSTS 0x20 62064520e8SBard Liao #define MTL_DSP_IRQSTS_IPC BIT(0) 63064520e8SBard Liao #define MTL_DSP_IRQSTS_SDW BIT(6) 64064520e8SBard Liao 65064520e8SBard Liao #define MTL_DSP_REG_POLL_INTERVAL_US 10 /* 10 us */ 66064520e8SBard Liao 67064520e8SBard Liao /* Memory windows */ 68064520e8SBard Liao #define MTL_SRAM_WINDOW_OFFSET(x) (0x180000 + 0x8000 * (x)) 69064520e8SBard Liao 70064520e8SBard Liao #define MTL_DSP_MBOX_UPLINK_OFFSET (MTL_SRAM_WINDOW_OFFSET(0) + 0x1000) 71064520e8SBard Liao #define MTL_DSP_MBOX_UPLINK_SIZE 0x1000 72064520e8SBard Liao #define MTL_DSP_MBOX_DOWNLINK_OFFSET MTL_SRAM_WINDOW_OFFSET(1) 73064520e8SBard Liao #define MTL_DSP_MBOX_DOWNLINK_SIZE 0x1000 74064520e8SBard Liao 75064520e8SBard Liao /* FW registers */ 76064520e8SBard Liao #define MTL_DSP_ROM_STS MTL_SRAM_WINDOW_OFFSET(0) /* ROM status */ 77064520e8SBard Liao #define MTL_DSP_ROM_ERROR (MTL_SRAM_WINDOW_OFFSET(0) + 0x4) /* ROM error code */ 78064520e8SBard Liao 798aeb3dc8SPeter Ujfalusi #define MTL_DSP_REG_HFFLGPXQWY 0x163200 /* DSP core0 status */ 808aeb3dc8SPeter Ujfalusi #define MTL_DSP_REG_HFFLGPXQWY_ERROR 0x163204 /* DSP core0 error */ 81064520e8SBard Liao #define MTL_DSP_REG_HfIMRIS1 0x162088 82064520e8SBard Liao #define MTL_DSP_REG_HfIMRIS1_IU_MASK BIT(0) 83064520e8SBard Liao 84c22d5327SPierre-Louis Bossart bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev); 85c22d5327SPierre-Louis Bossart int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg); 86c22d5327SPierre-Louis Bossart 87730025cfSPierre-Louis Bossart void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev); 88730025cfSPierre-Louis Bossart void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev); 89730025cfSPierre-Louis Bossart 90730025cfSPierre-Louis Bossart int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable); 91c22d5327SPierre-Louis Bossart 92c22d5327SPierre-Louis Bossart int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev); 93c22d5327SPierre-Louis Bossart int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev); 94c22d5327SPierre-Louis Bossart void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags); 95c22d5327SPierre-Louis Bossart 96730025cfSPierre-Louis Bossart int mtl_power_down_dsp(struct snd_sof_dev *sdev); 97c22d5327SPierre-Louis Bossart int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot); 98c22d5327SPierre-Louis Bossart 99c22d5327SPierre-Louis Bossart irqreturn_t mtl_ipc_irq_thread(int irq, void *context); 100c22d5327SPierre-Louis Bossart 101c22d5327SPierre-Louis Bossart int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 102c22d5327SPierre-Louis Bossart int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 103c22d5327SPierre-Louis Bossart 104c22d5327SPierre-Louis Bossart void mtl_ipc_dump(struct snd_sof_dev *sdev); 105c22d5327SPierre-Louis Bossart 106c22d5327SPierre-Louis Bossart u64 mtl_dsp_get_stream_hda_link_position(struct snd_sof_dev *sdev, 107c22d5327SPierre-Louis Bossart struct snd_soc_component *component, 108c22d5327SPierre-Louis Bossart struct snd_pcm_substream *substream); 109