| /openbmc/u-boot/drivers/rtc/ |
| H A D | rx8025.c | 81 uchar sec, min, hour, mday, wday, mon, year, ctl2; in rtc_get() local
100 ctl2 = rtc_read(RTC_CTL2_REG_ADDR); in rtc_get()
101 if (ctl2 & RTC_CTL2_BIT_PON) { in rtc_get()
106 if (ctl2 & RTC_CTL2_BIT_VDET) { in rtc_get()
111 if (!(ctl2 & RTC_CTL2_BIT_XST)) { in rtc_get()
168 uchar ctl2; in rtc_reset() local
173 ctl2 = rtc_read(RTC_CTL2_REG_ADDR); in rtc_reset()
174 ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET); in rtc_reset()
175 ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL; in rtc_reset()
176 rtc_write (RTC_CTL2_REG_ADDR, ctl2); in rtc_reset()
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| /openbmc/linux/tools/testing/selftests/kvm/x86_64/ |
| H A D | ucna_injection_test.c | 82 uint64_t ctl2; in ucna_injection_guest_code() local
88 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in ucna_injection_guest_code()
89 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN); in ucna_injection_guest_code()
100 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in ucna_injection_guest_code()
101 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 & ~MCI_CTL2_CMCI_EN); in ucna_injection_guest_code()
112 uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in cmci_disabled_guest_code() local
113 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN); in cmci_disabled_guest_code()
120 uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK)); in cmci_enabled_guest_code() local
121 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_RESERVED_BIT); in cmci_enabled_guest_code()
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| /openbmc/u-boot/board/freescale/ls2080a/ |
| H A D | ddr.h | 28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
40 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
51 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
64 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
|
| /openbmc/u-boot/board/freescale/ls2080aqds/ |
| H A D | ddr.h | 28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
42 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
55 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
69 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
|
| /openbmc/u-boot/board/freescale/ls2080ardb/ |
| H A D | ddr.h | 28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
42 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
55 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
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| /openbmc/linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_backlight.c | 603 u32 ctl, ctl2, freq; in i965_enable_backlight() local
605 ctl2 = intel_de_read(i915, BLC_PWM_CTL2); in i965_enable_backlight()
606 if (ctl2 & BLM_PWM_ENABLE) { in i965_enable_backlight()
609 ctl2 &= ~BLM_PWM_ENABLE; in i965_enable_backlight()
610 intel_de_write(i915, BLC_PWM_CTL2, ctl2); in i965_enable_backlight()
620 ctl2 = BLM_PIPE(pipe); in i965_enable_backlight()
622 ctl2 |= BLM_COMBINATION_MODE; in i965_enable_backlight()
624 ctl2 |= BLM_POLARITY_I965; in i965_enable_backlight()
625 intel_de_write(i915, BLC_PWM_CTL2, ctl2); in i965_enable_backlight()
627 intel_de_write(i915, BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); in i965_enable_backlight()
[all …]
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| H A D | dvo_tfp410.c | 207 u8 ctl2; in tfp410_detect() local
209 if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) { in tfp410_detect()
210 if (ctl2 & TFP410_CTL_2_RSEN) in tfp410_detect()
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| /openbmc/qemu/tests/qtest/ |
| H A D | npcm7xx_smbus-test.c | 118 /* CTL2 fields */
197 uint8_t ctl2 = qtest_readb(qts, base_addr + OFFSET_CTL2); in enable_bus() local
199 ctl2 |= CTL2_ENABLE; in enable_bus()
200 qtest_writeb(qts, base_addr + OFFSET_CTL2, ctl2); in enable_bus()
206 uint8_t ctl2 = qtest_readb(qts, base_addr + OFFSET_CTL2); in disable_bus() local
208 ctl2 &= ~CTL2_ENABLE; in disable_bus()
209 qtest_writeb(qts, base_addr + OFFSET_CTL2, ctl2); in disable_bus()
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | cafe_nand.c | 66 uint32_t ctl2; member
174 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2); in cafe_nand_cmdfunc()
176 cafe->ctl2 &= ~(1<<30); in cafe_nand_cmdfunc()
243 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2); in cafe_nand_cmdfunc()
245 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2); in cafe_nand_cmdfunc()
248 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n", in cafe_nand_cmdfunc()
298 WARN_ON(cafe->ctl2 & (1<<30)); in cafe_nand_cmdfunc()
310 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); in cafe_nand_cmdfunc()
314 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); in cafe_nand_cmdfunc()
544 cafe->ctl2 |= (1<<30); in cafe_nand_write_page_lowlevel()
[all …]
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| /openbmc/linux/drivers/rtc/ |
| H A D | rtc-rs5c348.c | 79 txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_set_time()
81 txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_set_time()
124 txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_read_time()
126 txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */ in rs5c348_rtc_read_time()
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| H A D | rtc-rzn1.c | 274 u32 subu = 0, ctl2; in rzn1_rtc_set_offset() local
308 ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, ctl2, in rzn1_rtc_set_offset()
309 !(ctl2 & RZN1_RTC_CTL2_WUST), 100, 2000000); in rzn1_rtc_set_offset()
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| /openbmc/u-boot/board/freescale/ls1046ardb/ |
| H A D | ddr.h | 30 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
47 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
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| /openbmc/u-boot/board/freescale/t208xqds/ |
| H A D | ddr.h | 28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
48 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
|
| /openbmc/qemu/include/hw/i2c/ |
| H A D | npcm7xx_smbus.h | 52 * @ctl2: The control register 2.
85 uint8_t ctl2; member
|
| /openbmc/u-boot/board/freescale/t4rdb/ |
| H A D | ddr.h | 27 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
46 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
|
| /openbmc/u-boot/board/freescale/t4qds/ |
| H A D | ddr.h | 31 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
50 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
|
| /openbmc/linux/drivers/hwmon/ |
| H A D | lm93.c | 291 * The two PWM CTL2 registers can read something other than what was
1752 u8 ctl2, ctl4; in pwm_show() local
1755 ctl2 = data->block9[nr][LM93_PWM_CTL2]; in pwm_show()
1757 if (ctl2 & 0x01) /* show user commanded value if enabled */ in pwm_show()
1760 rc = LM93_PWM_FROM_REG(ctl2 >> 4, (ctl4 & 0x07) ? in pwm_show()
1771 u8 ctl2, ctl4; in pwm_store() local
1780 ctl2 = lm93_read_byte(client, LM93_REG_PWM_CTL(nr, LM93_PWM_CTL2)); in pwm_store()
1782 ctl2 = (ctl2 & 0x0f) | LM93_PWM_TO_REG(val, (ctl4 & 0x07) ? in pwm_store()
1785 data->pwm_override[nr] = LM93_PWM_FROM_REG(ctl2 >> 4, in pwm_store()
1788 lm93_write_byte(client, LM93_REG_PWM_CTL(nr, LM93_PWM_CTL2), ctl2); in pwm_store()
[all …]
|
| /openbmc/u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | xhci-keystone.h | 16 unsigned int phy_param_ctrl_1; /* ctl2 */
|
| /openbmc/u-boot/board/freescale/ls1046aqds/ |
| H A D | ddr.h | 30 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
|
| /openbmc/qemu/hw/i2c/ |
| H A D | npcm7xx_smbus.c | 115 /* CTL2 fields */
164 #define NPCM7XX_SMBUS_ENABLED(s) ((s)->ctl2 & NPCM7XX_SMBCTL2_ENABLE)
571 s->ctl2 = value; in npcm7xx_smbus_write_ctl2()
685 value = s->ctl2; in npcm7xx_smbus_read()
1000 s->ctl2 = NPCM7XX_SMB_CTL2_INIT_VAL; in npcm7xx_smbus_enter_reset()
1056 VMSTATE_UINT8(ctl2, NPCM7xxSMBusState),
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| /openbmc/u-boot/board/freescale/ls1088a/ |
| H A D | ddr.h | 28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3
|
| /openbmc/u-boot/board/freescale/t208xrdb/ |
| H A D | ddr.h | 28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
|
| /openbmc/u-boot/board/freescale/t1040qds/ |
| H A D | ddr.h | 28 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
|
| /openbmc/linux/drivers/video/fbdev/ |
| H A D | arcfb.c | 427 unsigned char ctl2; in arcfb_ioctl() local
429 ctl2 = ks108_readb_ctl2(info->par); in arcfb_ioctl()
430 if (copy_to_user(argp, &ctl2, sizeof(ctl2))) in arcfb_ioctl()
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| /openbmc/u-boot/board/freescale/t104xrdb/ |
| H A D | ddr.h | 28 * ranks| mhz| GB |adjst| start | ctl2
|