1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
295c6bc7dSMatthias Fuchs /*
395c6bc7dSMatthias Fuchs * (C) Copyright 2007
495c6bc7dSMatthias Fuchs * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
595c6bc7dSMatthias Fuchs */
695c6bc7dSMatthias Fuchs
795c6bc7dSMatthias Fuchs /*
895c6bc7dSMatthias Fuchs * Epson RX8025 RTC driver.
995c6bc7dSMatthias Fuchs */
1095c6bc7dSMatthias Fuchs
1195c6bc7dSMatthias Fuchs #include <common.h>
1295c6bc7dSMatthias Fuchs #include <command.h>
1395c6bc7dSMatthias Fuchs #include <rtc.h>
1495c6bc7dSMatthias Fuchs #include <i2c.h>
1595c6bc7dSMatthias Fuchs
1695c6bc7dSMatthias Fuchs /*---------------------------------------------------------------------*/
1795c6bc7dSMatthias Fuchs #undef DEBUG_RTC
1895c6bc7dSMatthias Fuchs
1995c6bc7dSMatthias Fuchs #ifdef DEBUG_RTC
2095c6bc7dSMatthias Fuchs #define DEBUGR(fmt,args...) printf(fmt ,##args)
2195c6bc7dSMatthias Fuchs #else
2295c6bc7dSMatthias Fuchs #define DEBUGR(fmt,args...)
2395c6bc7dSMatthias Fuchs #endif
2495c6bc7dSMatthias Fuchs /*---------------------------------------------------------------------*/
2595c6bc7dSMatthias Fuchs
266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_I2C_RTC_ADDR
276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_I2C_RTC_ADDR 0x32
2895c6bc7dSMatthias Fuchs #endif
2995c6bc7dSMatthias Fuchs
3095c6bc7dSMatthias Fuchs /*
3195c6bc7dSMatthias Fuchs * RTC register addresses
3295c6bc7dSMatthias Fuchs */
3395c6bc7dSMatthias Fuchs #define RTC_SEC_REG_ADDR 0x00
3495c6bc7dSMatthias Fuchs #define RTC_MIN_REG_ADDR 0x01
3595c6bc7dSMatthias Fuchs #define RTC_HR_REG_ADDR 0x02
3695c6bc7dSMatthias Fuchs #define RTC_DAY_REG_ADDR 0x03
3795c6bc7dSMatthias Fuchs #define RTC_DATE_REG_ADDR 0x04
3895c6bc7dSMatthias Fuchs #define RTC_MON_REG_ADDR 0x05
3995c6bc7dSMatthias Fuchs #define RTC_YR_REG_ADDR 0x06
4095c6bc7dSMatthias Fuchs
4195c6bc7dSMatthias Fuchs #define RTC_CTL1_REG_ADDR 0x0e
4295c6bc7dSMatthias Fuchs #define RTC_CTL2_REG_ADDR 0x0f
4395c6bc7dSMatthias Fuchs
4495c6bc7dSMatthias Fuchs /*
4595c6bc7dSMatthias Fuchs * Control register 1 bits
4695c6bc7dSMatthias Fuchs */
4795c6bc7dSMatthias Fuchs #define RTC_CTL1_BIT_2412 0x20
4895c6bc7dSMatthias Fuchs
4995c6bc7dSMatthias Fuchs /*
5095c6bc7dSMatthias Fuchs * Control register 2 bits
5195c6bc7dSMatthias Fuchs */
5295c6bc7dSMatthias Fuchs #define RTC_CTL2_BIT_PON 0x10
5395c6bc7dSMatthias Fuchs #define RTC_CTL2_BIT_VDET 0x40
5495c6bc7dSMatthias Fuchs #define RTC_CTL2_BIT_XST 0x20
5595c6bc7dSMatthias Fuchs #define RTC_CTL2_BIT_VDSL 0x80
5695c6bc7dSMatthias Fuchs
5795c6bc7dSMatthias Fuchs /*
5895c6bc7dSMatthias Fuchs * Note: the RX8025 I2C RTC requires register
5995c6bc7dSMatthias Fuchs * reads and write to consist of a single bus
6095c6bc7dSMatthias Fuchs * cycle. It is not allowed to write the register
6195c6bc7dSMatthias Fuchs * address in a first cycle that is terminated by
6295c6bc7dSMatthias Fuchs * a STOP condition. The chips needs a 'restart'
6395c6bc7dSMatthias Fuchs * sequence (start sequence without a prior stop).
6495c6bc7dSMatthias Fuchs * This driver has been written for a 4xx board.
6595c6bc7dSMatthias Fuchs * U-Boot's 4xx i2c driver is currently not capable
6695c6bc7dSMatthias Fuchs * to generate such cycles to some work arounds
6795c6bc7dSMatthias Fuchs * are used.
6895c6bc7dSMatthias Fuchs */
6995c6bc7dSMatthias Fuchs
7095c6bc7dSMatthias Fuchs /* static uchar rtc_read (uchar reg); */
7195c6bc7dSMatthias Fuchs #define rtc_read(reg) buf[((reg) + 1) & 0xf]
7295c6bc7dSMatthias Fuchs
7395c6bc7dSMatthias Fuchs static void rtc_write (uchar reg, uchar val);
7495c6bc7dSMatthias Fuchs
7595c6bc7dSMatthias Fuchs /*
7695c6bc7dSMatthias Fuchs * Get the current time from the RTC
7795c6bc7dSMatthias Fuchs */
rtc_get(struct rtc_time * tmp)78b73a19e1SYuri Tikhonov int rtc_get (struct rtc_time *tmp)
7995c6bc7dSMatthias Fuchs {
80b73a19e1SYuri Tikhonov int rel = 0;
8195c6bc7dSMatthias Fuchs uchar sec, min, hour, mday, wday, mon, year, ctl2;
8295c6bc7dSMatthias Fuchs uchar buf[16];
8395c6bc7dSMatthias Fuchs
846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16))
8595c6bc7dSMatthias Fuchs printf("Error reading from RTC\n");
8695c6bc7dSMatthias Fuchs
8795c6bc7dSMatthias Fuchs sec = rtc_read(RTC_SEC_REG_ADDR);
8895c6bc7dSMatthias Fuchs min = rtc_read(RTC_MIN_REG_ADDR);
8995c6bc7dSMatthias Fuchs hour = rtc_read(RTC_HR_REG_ADDR);
9095c6bc7dSMatthias Fuchs wday = rtc_read(RTC_DAY_REG_ADDR);
9195c6bc7dSMatthias Fuchs mday = rtc_read(RTC_DATE_REG_ADDR);
9295c6bc7dSMatthias Fuchs mon = rtc_read(RTC_MON_REG_ADDR);
9395c6bc7dSMatthias Fuchs year = rtc_read(RTC_YR_REG_ADDR);
9495c6bc7dSMatthias Fuchs
9595c6bc7dSMatthias Fuchs DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
9695c6bc7dSMatthias Fuchs "hr: %02x min: %02x sec: %02x\n",
9795c6bc7dSMatthias Fuchs year, mon, mday, wday, hour, min, sec);
9895c6bc7dSMatthias Fuchs
9995c6bc7dSMatthias Fuchs /* dump status */
10095c6bc7dSMatthias Fuchs ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
101b73a19e1SYuri Tikhonov if (ctl2 & RTC_CTL2_BIT_PON) {
10295c6bc7dSMatthias Fuchs printf("RTC: power-on detected\n");
103b73a19e1SYuri Tikhonov rel = -1;
104b73a19e1SYuri Tikhonov }
10595c6bc7dSMatthias Fuchs
106b73a19e1SYuri Tikhonov if (ctl2 & RTC_CTL2_BIT_VDET) {
10795c6bc7dSMatthias Fuchs printf("RTC: voltage drop detected\n");
108b73a19e1SYuri Tikhonov rel = -1;
109b73a19e1SYuri Tikhonov }
11095c6bc7dSMatthias Fuchs
111b73a19e1SYuri Tikhonov if (!(ctl2 & RTC_CTL2_BIT_XST)) {
11295c6bc7dSMatthias Fuchs printf("RTC: oscillator stop detected\n");
113b73a19e1SYuri Tikhonov rel = -1;
114b73a19e1SYuri Tikhonov }
11595c6bc7dSMatthias Fuchs
11695c6bc7dSMatthias Fuchs tmp->tm_sec = bcd2bin (sec & 0x7F);
11795c6bc7dSMatthias Fuchs tmp->tm_min = bcd2bin (min & 0x7F);
1185875d358SYuri Tikhonov if (rtc_read(RTC_CTL1_REG_ADDR) & RTC_CTL1_BIT_2412)
11995c6bc7dSMatthias Fuchs tmp->tm_hour = bcd2bin (hour & 0x3F);
1205875d358SYuri Tikhonov else
1215875d358SYuri Tikhonov tmp->tm_hour = bcd2bin (hour & 0x1F) % 12 +
1225875d358SYuri Tikhonov ((hour & 0x20) ? 12 : 0);
12395c6bc7dSMatthias Fuchs tmp->tm_mday = bcd2bin (mday & 0x3F);
12495c6bc7dSMatthias Fuchs tmp->tm_mon = bcd2bin (mon & 0x1F);
12595c6bc7dSMatthias Fuchs tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
12695c6bc7dSMatthias Fuchs tmp->tm_wday = bcd2bin (wday & 0x07);
12795c6bc7dSMatthias Fuchs tmp->tm_yday = 0;
12895c6bc7dSMatthias Fuchs tmp->tm_isdst= 0;
12995c6bc7dSMatthias Fuchs
13095c6bc7dSMatthias Fuchs DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
13195c6bc7dSMatthias Fuchs tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
13295c6bc7dSMatthias Fuchs tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
133b73a19e1SYuri Tikhonov
134b73a19e1SYuri Tikhonov return rel;
13595c6bc7dSMatthias Fuchs }
13695c6bc7dSMatthias Fuchs
13795c6bc7dSMatthias Fuchs /*
13895c6bc7dSMatthias Fuchs * Set the RTC
13995c6bc7dSMatthias Fuchs */
rtc_set(struct rtc_time * tmp)140d1e23194SJean-Christophe PLAGNIOL-VILLARD int rtc_set (struct rtc_time *tmp)
14195c6bc7dSMatthias Fuchs {
14295c6bc7dSMatthias Fuchs DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
14395c6bc7dSMatthias Fuchs tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
14495c6bc7dSMatthias Fuchs tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
14595c6bc7dSMatthias Fuchs
14695c6bc7dSMatthias Fuchs if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
14795c6bc7dSMatthias Fuchs printf("WARNING: year should be between 1970 and 2069!\n");
14895c6bc7dSMatthias Fuchs
14995c6bc7dSMatthias Fuchs rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
15095c6bc7dSMatthias Fuchs rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
15195c6bc7dSMatthias Fuchs rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday));
15295c6bc7dSMatthias Fuchs rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
15395c6bc7dSMatthias Fuchs rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
15495c6bc7dSMatthias Fuchs rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
15595c6bc7dSMatthias Fuchs rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
15695c6bc7dSMatthias Fuchs
15795c6bc7dSMatthias Fuchs rtc_write (RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
158d1e23194SJean-Christophe PLAGNIOL-VILLARD
159d1e23194SJean-Christophe PLAGNIOL-VILLARD return 0;
16095c6bc7dSMatthias Fuchs }
16195c6bc7dSMatthias Fuchs
16295c6bc7dSMatthias Fuchs /*
163402c8fd5SChris Packham * Reset the RTC
16495c6bc7dSMatthias Fuchs */
rtc_reset(void)16595c6bc7dSMatthias Fuchs void rtc_reset (void)
16695c6bc7dSMatthias Fuchs {
16795c6bc7dSMatthias Fuchs uchar buf[16];
16895c6bc7dSMatthias Fuchs uchar ctl2;
16995c6bc7dSMatthias Fuchs
1706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16))
17195c6bc7dSMatthias Fuchs printf("Error reading from RTC\n");
17295c6bc7dSMatthias Fuchs
17395c6bc7dSMatthias Fuchs ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
17495c6bc7dSMatthias Fuchs ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET);
17595c6bc7dSMatthias Fuchs ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL;
17695c6bc7dSMatthias Fuchs rtc_write (RTC_CTL2_REG_ADDR, ctl2);
17795c6bc7dSMatthias Fuchs }
17895c6bc7dSMatthias Fuchs
17995c6bc7dSMatthias Fuchs /*
18095c6bc7dSMatthias Fuchs * Helper functions
18195c6bc7dSMatthias Fuchs */
rtc_write(uchar reg,uchar val)18295c6bc7dSMatthias Fuchs static void rtc_write (uchar reg, uchar val)
18395c6bc7dSMatthias Fuchs {
18495c6bc7dSMatthias Fuchs uchar buf[2];
18595c6bc7dSMatthias Fuchs buf[0] = reg << 4;
18695c6bc7dSMatthias Fuchs buf[1] = val;
1876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 2) != 0)
18895c6bc7dSMatthias Fuchs printf("Error writing to RTC\n");
18995c6bc7dSMatthias Fuchs
19095c6bc7dSMatthias Fuchs }
191