1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 27d436078SPrabhakar Kushwaha /* 3c60dee03SYork Sun * Copyright 2013-2014 Freescale Semiconductor, Inc. 47d436078SPrabhakar Kushwaha */ 57d436078SPrabhakar Kushwaha 67d436078SPrabhakar Kushwaha #ifndef __DDR_H__ 77d436078SPrabhakar Kushwaha #define __DDR_H__ 87d436078SPrabhakar Kushwaha struct board_specific_parameters { 97d436078SPrabhakar Kushwaha u32 n_ranks; 107d436078SPrabhakar Kushwaha u32 datarate_mhz_high; 117d436078SPrabhakar Kushwaha u32 rank_gb; 127d436078SPrabhakar Kushwaha u32 clk_adjust; 137d436078SPrabhakar Kushwaha u32 wrlvl_start; 147d436078SPrabhakar Kushwaha u32 wrlvl_ctl_2; 157d436078SPrabhakar Kushwaha u32 wrlvl_ctl_3; 167d436078SPrabhakar Kushwaha }; 177d436078SPrabhakar Kushwaha 187d436078SPrabhakar Kushwaha /* 197d436078SPrabhakar Kushwaha * These tables contain all valid speeds we want to override with board 207d436078SPrabhakar Kushwaha * specific parameters. datarate_mhz_high values need to be in ascending order 217d436078SPrabhakar Kushwaha * for each n_ranks group. 227d436078SPrabhakar Kushwaha */ 237d436078SPrabhakar Kushwaha 247d436078SPrabhakar Kushwaha static const struct board_specific_parameters udimm0[] = { 257d436078SPrabhakar Kushwaha /* 267d436078SPrabhakar Kushwaha * memory controller 0 27c60dee03SYork Sun * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | 28c60dee03SYork Sun * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | 297d436078SPrabhakar Kushwaha */ 30c60dee03SYork Sun #ifdef CONFIG_SYS_FSL_DDR4 31e04f9d0cSShengzhou Liu {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, 32e04f9d0cSShengzhou Liu {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, 33e04f9d0cSShengzhou Liu {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, 34e04f9d0cSShengzhou Liu {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, 35e04f9d0cSShengzhou Liu {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,}, 36c60dee03SYork Sun #elif defined(CONFIG_SYS_FSL_DDR3) 37e04f9d0cSShengzhou Liu {2, 833, 0, 8, 6, 0x06060607, 0x08080807,}, 38e04f9d0cSShengzhou Liu {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, 39e04f9d0cSShengzhou Liu {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, 40e04f9d0cSShengzhou Liu {1, 833, 0, 8, 6, 0x06060607, 0x08080807,}, 41e04f9d0cSShengzhou Liu {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, 42e04f9d0cSShengzhou Liu {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, 43c60dee03SYork Sun #else 44c60dee03SYork Sun #error DDR type not defined 45c60dee03SYork Sun #endif 467d436078SPrabhakar Kushwaha {} 477d436078SPrabhakar Kushwaha }; 487d436078SPrabhakar Kushwaha 497d436078SPrabhakar Kushwaha static const struct board_specific_parameters *udimms[] = { 507d436078SPrabhakar Kushwaha udimm0, 517d436078SPrabhakar Kushwaha }; 527d436078SPrabhakar Kushwaha #endif 53