1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2126fe70dSShaohui Xie /* 3126fe70dSShaohui Xie * Copyright 2016 Freescale Semiconductor, Inc. 4126fe70dSShaohui Xie */ 5126fe70dSShaohui Xie 6126fe70dSShaohui Xie #ifndef __DDR_H__ 7126fe70dSShaohui Xie #define __DDR_H__ 8126fe70dSShaohui Xie 9126fe70dSShaohui Xie void erratum_a008850_post(void); 10126fe70dSShaohui Xie 11126fe70dSShaohui Xie struct board_specific_parameters { 12126fe70dSShaohui Xie u32 n_ranks; 13126fe70dSShaohui Xie u32 datarate_mhz_high; 14126fe70dSShaohui Xie u32 rank_gb; 15126fe70dSShaohui Xie u32 clk_adjust; 16126fe70dSShaohui Xie u32 wrlvl_start; 17126fe70dSShaohui Xie u32 wrlvl_ctl_2; 18126fe70dSShaohui Xie u32 wrlvl_ctl_3; 19126fe70dSShaohui Xie }; 20126fe70dSShaohui Xie 21126fe70dSShaohui Xie /* 22126fe70dSShaohui Xie * These tables contain all valid speeds we want to override with board 23126fe70dSShaohui Xie * specific parameters. datarate_mhz_high values need to be in ascending order 24126fe70dSShaohui Xie * for each n_ranks group. 25126fe70dSShaohui Xie */ 26126fe70dSShaohui Xie static const struct board_specific_parameters udimm0[] = { 27126fe70dSShaohui Xie /* 28126fe70dSShaohui Xie * memory controller 0 29126fe70dSShaohui Xie * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | 30126fe70dSShaohui Xie * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | 31126fe70dSShaohui Xie */ 32126fe70dSShaohui Xie {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, 33126fe70dSShaohui Xie {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, 34126fe70dSShaohui Xie {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, 35126fe70dSShaohui Xie {2, 2300, 0, 8, 9, 0x0A0C0D11, 0x1214150E,}, 36126fe70dSShaohui Xie {} 37126fe70dSShaohui Xie }; 38126fe70dSShaohui Xie 39126fe70dSShaohui Xie static const struct board_specific_parameters *udimms[] = { 40126fe70dSShaohui Xie udimm0, 41126fe70dSShaohui Xie }; 42126fe70dSShaohui Xie 43126fe70dSShaohui Xie #endif 44