1eede2065SJue Wang // SPDX-License-Identifier: GPL-2.0
2eede2065SJue Wang /*
3eede2065SJue Wang * ucna_injection_test
4eede2065SJue Wang *
5eede2065SJue Wang * Copyright (C) 2022, Google LLC.
6eede2065SJue Wang *
7eede2065SJue Wang * This work is licensed under the terms of the GNU GPL, version 2.
8eede2065SJue Wang *
9eede2065SJue Wang * Test that user space can inject UnCorrectable No Action required (UCNA)
10eede2065SJue Wang * memory errors to the guest.
11eede2065SJue Wang *
12eede2065SJue Wang * The test starts one vCPU with the MCG_CMCI_P enabled. It verifies that
13eede2065SJue Wang * proper UCNA errors can be injected to a vCPU with MCG_CMCI_P and
14eede2065SJue Wang * corresponding per-bank control register (MCI_CTL2) bit enabled.
15eede2065SJue Wang * The test also checks that the UCNA errors get recorded in the
16eede2065SJue Wang * Machine Check bank registers no matter the error signal interrupts get
17eede2065SJue Wang * delivered into the guest or not.
18eede2065SJue Wang *
19eede2065SJue Wang */
20eede2065SJue Wang
21eede2065SJue Wang #define _GNU_SOURCE /* for program_invocation_short_name */
22eede2065SJue Wang #include <pthread.h>
23eede2065SJue Wang #include <inttypes.h>
24eede2065SJue Wang #include <string.h>
25eede2065SJue Wang #include <time.h>
26eede2065SJue Wang
27eede2065SJue Wang #include "kvm_util_base.h"
28eede2065SJue Wang #include "kvm_util.h"
29eede2065SJue Wang #include "mce.h"
30eede2065SJue Wang #include "processor.h"
31eede2065SJue Wang #include "test_util.h"
32eede2065SJue Wang #include "apic.h"
33eede2065SJue Wang
34eede2065SJue Wang #define SYNC_FIRST_UCNA 9
35eede2065SJue Wang #define SYNC_SECOND_UCNA 10
36eede2065SJue Wang #define SYNC_GP 11
37eede2065SJue Wang #define FIRST_UCNA_ADDR 0xdeadbeef
38eede2065SJue Wang #define SECOND_UCNA_ADDR 0xcafeb0ba
39eede2065SJue Wang
40eede2065SJue Wang /*
41eede2065SJue Wang * Vector for the CMCI interrupt.
42eede2065SJue Wang * Value is arbitrary. Any value in 0x20-0xFF should work:
43eede2065SJue Wang * https://wiki.osdev.org/Interrupt_Vector_Table
44eede2065SJue Wang */
45eede2065SJue Wang #define CMCI_VECTOR 0xa9
46eede2065SJue Wang
47eede2065SJue Wang #define UCNA_BANK 0x7 // IMC0 bank
48eede2065SJue Wang
49eede2065SJue Wang #define MCI_CTL2_RESERVED_BIT BIT_ULL(29)
50eede2065SJue Wang
51eede2065SJue Wang static uint64_t supported_mcg_caps;
52eede2065SJue Wang
53eede2065SJue Wang /*
54eede2065SJue Wang * Record states about the injected UCNA.
55eede2065SJue Wang * The variables started with the 'i_' prefixes are recorded in interrupt
56eede2065SJue Wang * handler. Variables without the 'i_' prefixes are recorded in guest main
57eede2065SJue Wang * execution thread.
58eede2065SJue Wang */
59eede2065SJue Wang static volatile uint64_t i_ucna_rcvd;
60eede2065SJue Wang static volatile uint64_t i_ucna_addr;
61eede2065SJue Wang static volatile uint64_t ucna_addr;
62eede2065SJue Wang static volatile uint64_t ucna_addr2;
63eede2065SJue Wang
64eede2065SJue Wang struct thread_params {
65eede2065SJue Wang struct kvm_vcpu *vcpu;
66eede2065SJue Wang uint64_t *p_i_ucna_rcvd;
67eede2065SJue Wang uint64_t *p_i_ucna_addr;
68eede2065SJue Wang uint64_t *p_ucna_addr;
69eede2065SJue Wang uint64_t *p_ucna_addr2;
70eede2065SJue Wang };
71eede2065SJue Wang
verify_apic_base_addr(void)72eede2065SJue Wang static void verify_apic_base_addr(void)
73eede2065SJue Wang {
74eede2065SJue Wang uint64_t msr = rdmsr(MSR_IA32_APICBASE);
75eede2065SJue Wang uint64_t base = GET_APIC_BASE(msr);
76eede2065SJue Wang
77eede2065SJue Wang GUEST_ASSERT(base == APIC_DEFAULT_GPA);
78eede2065SJue Wang }
79eede2065SJue Wang
ucna_injection_guest_code(void)80eede2065SJue Wang static void ucna_injection_guest_code(void)
81eede2065SJue Wang {
82eede2065SJue Wang uint64_t ctl2;
83eede2065SJue Wang verify_apic_base_addr();
84eede2065SJue Wang xapic_enable();
85eede2065SJue Wang
86eede2065SJue Wang /* Sets up the interrupt vector and enables per-bank CMCI sigaling. */
87eede2065SJue Wang xapic_write_reg(APIC_LVTCMCI, CMCI_VECTOR | APIC_DM_FIXED);
88eede2065SJue Wang ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
89eede2065SJue Wang wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN);
90eede2065SJue Wang
91eede2065SJue Wang /* Enables interrupt in guest. */
92eede2065SJue Wang asm volatile("sti");
93eede2065SJue Wang
94eede2065SJue Wang /* Let user space inject the first UCNA */
95eede2065SJue Wang GUEST_SYNC(SYNC_FIRST_UCNA);
96eede2065SJue Wang
97eede2065SJue Wang ucna_addr = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK));
98eede2065SJue Wang
99eede2065SJue Wang /* Disables the per-bank CMCI signaling. */
100eede2065SJue Wang ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
101eede2065SJue Wang wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 & ~MCI_CTL2_CMCI_EN);
102eede2065SJue Wang
103eede2065SJue Wang /* Let the user space inject the second UCNA */
104eede2065SJue Wang GUEST_SYNC(SYNC_SECOND_UCNA);
105eede2065SJue Wang
106eede2065SJue Wang ucna_addr2 = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK));
107eede2065SJue Wang GUEST_DONE();
108eede2065SJue Wang }
109eede2065SJue Wang
cmci_disabled_guest_code(void)110eede2065SJue Wang static void cmci_disabled_guest_code(void)
111eede2065SJue Wang {
112eede2065SJue Wang uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
113eede2065SJue Wang wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN);
114eede2065SJue Wang
115eede2065SJue Wang GUEST_DONE();
116eede2065SJue Wang }
117eede2065SJue Wang
cmci_enabled_guest_code(void)118eede2065SJue Wang static void cmci_enabled_guest_code(void)
119eede2065SJue Wang {
120eede2065SJue Wang uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
121eede2065SJue Wang wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_RESERVED_BIT);
122eede2065SJue Wang
123eede2065SJue Wang GUEST_DONE();
124eede2065SJue Wang }
125eede2065SJue Wang
guest_cmci_handler(struct ex_regs * regs)126eede2065SJue Wang static void guest_cmci_handler(struct ex_regs *regs)
127eede2065SJue Wang {
128eede2065SJue Wang i_ucna_rcvd++;
129eede2065SJue Wang i_ucna_addr = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK));
130eede2065SJue Wang xapic_write_reg(APIC_EOI, 0);
131eede2065SJue Wang }
132eede2065SJue Wang
guest_gp_handler(struct ex_regs * regs)133eede2065SJue Wang static void guest_gp_handler(struct ex_regs *regs)
134eede2065SJue Wang {
135eede2065SJue Wang GUEST_SYNC(SYNC_GP);
136eede2065SJue Wang }
137eede2065SJue Wang
run_vcpu_expect_gp(struct kvm_vcpu * vcpu)138eede2065SJue Wang static void run_vcpu_expect_gp(struct kvm_vcpu *vcpu)
139eede2065SJue Wang {
140eede2065SJue Wang struct ucall uc;
141eede2065SJue Wang
142eede2065SJue Wang vcpu_run(vcpu);
143eede2065SJue Wang
144*c96f57b0SVipin Sharma TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO);
145eede2065SJue Wang TEST_ASSERT(get_ucall(vcpu, &uc) == UCALL_SYNC,
146eede2065SJue Wang "Expect UCALL_SYNC\n");
147eede2065SJue Wang TEST_ASSERT(uc.args[1] == SYNC_GP, "#GP is expected.");
148eede2065SJue Wang printf("vCPU received GP in guest.\n");
149eede2065SJue Wang }
150eede2065SJue Wang
inject_ucna(struct kvm_vcpu * vcpu,uint64_t addr)151eede2065SJue Wang static void inject_ucna(struct kvm_vcpu *vcpu, uint64_t addr) {
152eede2065SJue Wang /*
153eede2065SJue Wang * A UCNA error is indicated with VAL=1, UC=1, PCC=0, S=0 and AR=0 in
154eede2065SJue Wang * the IA32_MCi_STATUS register.
155eede2065SJue Wang * MSCOD=1 (BIT[16] - MscodDataRdErr).
156eede2065SJue Wang * MCACOD=0x0090 (Memory controller error format, channel 0)
157eede2065SJue Wang */
158eede2065SJue Wang uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
159eede2065SJue Wang MCI_STATUS_MISCV | MCI_STATUS_ADDRV | 0x10090;
160eede2065SJue Wang struct kvm_x86_mce mce = {};
161eede2065SJue Wang mce.status = status;
162eede2065SJue Wang mce.mcg_status = 0;
163eede2065SJue Wang /*
164eede2065SJue Wang * MCM_ADDR_PHYS indicates the reported address is a physical address.
165eede2065SJue Wang * Lowest 6 bits is the recoverable address LSB, i.e., the injected MCE
166eede2065SJue Wang * is at 4KB granularity.
167eede2065SJue Wang */
168eede2065SJue Wang mce.misc = (MCM_ADDR_PHYS << 6) | 0xc;
169eede2065SJue Wang mce.addr = addr;
170eede2065SJue Wang mce.bank = UCNA_BANK;
171eede2065SJue Wang
172eede2065SJue Wang vcpu_ioctl(vcpu, KVM_X86_SET_MCE, &mce);
173eede2065SJue Wang }
174eede2065SJue Wang
run_ucna_injection(void * arg)175eede2065SJue Wang static void *run_ucna_injection(void *arg)
176eede2065SJue Wang {
177eede2065SJue Wang struct thread_params *params = (struct thread_params *)arg;
178eede2065SJue Wang struct ucall uc;
179eede2065SJue Wang int old;
180eede2065SJue Wang int r;
181eede2065SJue Wang
182eede2065SJue Wang r = pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS, &old);
183eede2065SJue Wang TEST_ASSERT(r == 0,
184eede2065SJue Wang "pthread_setcanceltype failed with errno=%d",
185eede2065SJue Wang r);
186eede2065SJue Wang
187eede2065SJue Wang vcpu_run(params->vcpu);
188eede2065SJue Wang
189*c96f57b0SVipin Sharma TEST_ASSERT_KVM_EXIT_REASON(params->vcpu, KVM_EXIT_IO);
190eede2065SJue Wang TEST_ASSERT(get_ucall(params->vcpu, &uc) == UCALL_SYNC,
191eede2065SJue Wang "Expect UCALL_SYNC\n");
192eede2065SJue Wang TEST_ASSERT(uc.args[1] == SYNC_FIRST_UCNA, "Injecting first UCNA.");
193eede2065SJue Wang
194eede2065SJue Wang printf("Injecting first UCNA at %#x.\n", FIRST_UCNA_ADDR);
195eede2065SJue Wang
196eede2065SJue Wang inject_ucna(params->vcpu, FIRST_UCNA_ADDR);
197eede2065SJue Wang vcpu_run(params->vcpu);
198eede2065SJue Wang
199*c96f57b0SVipin Sharma TEST_ASSERT_KVM_EXIT_REASON(params->vcpu, KVM_EXIT_IO);
200eede2065SJue Wang TEST_ASSERT(get_ucall(params->vcpu, &uc) == UCALL_SYNC,
201eede2065SJue Wang "Expect UCALL_SYNC\n");
202eede2065SJue Wang TEST_ASSERT(uc.args[1] == SYNC_SECOND_UCNA, "Injecting second UCNA.");
203eede2065SJue Wang
204eede2065SJue Wang printf("Injecting second UCNA at %#x.\n", SECOND_UCNA_ADDR);
205eede2065SJue Wang
206eede2065SJue Wang inject_ucna(params->vcpu, SECOND_UCNA_ADDR);
207eede2065SJue Wang vcpu_run(params->vcpu);
208eede2065SJue Wang
209*c96f57b0SVipin Sharma TEST_ASSERT_KVM_EXIT_REASON(params->vcpu, KVM_EXIT_IO);
210eede2065SJue Wang if (get_ucall(params->vcpu, &uc) == UCALL_ABORT) {
211eede2065SJue Wang TEST_ASSERT(false, "vCPU assertion failure: %s.\n",
212eede2065SJue Wang (const char *)uc.args[0]);
213eede2065SJue Wang }
214eede2065SJue Wang
215eede2065SJue Wang return NULL;
216eede2065SJue Wang }
217eede2065SJue Wang
test_ucna_injection(struct kvm_vcpu * vcpu,struct thread_params * params)218eede2065SJue Wang static void test_ucna_injection(struct kvm_vcpu *vcpu, struct thread_params *params)
219eede2065SJue Wang {
220eede2065SJue Wang struct kvm_vm *vm = vcpu->vm;
221eede2065SJue Wang params->vcpu = vcpu;
222eede2065SJue Wang params->p_i_ucna_rcvd = (uint64_t *)addr_gva2hva(vm, (uint64_t)&i_ucna_rcvd);
223eede2065SJue Wang params->p_i_ucna_addr = (uint64_t *)addr_gva2hva(vm, (uint64_t)&i_ucna_addr);
224eede2065SJue Wang params->p_ucna_addr = (uint64_t *)addr_gva2hva(vm, (uint64_t)&ucna_addr);
225eede2065SJue Wang params->p_ucna_addr2 = (uint64_t *)addr_gva2hva(vm, (uint64_t)&ucna_addr2);
226eede2065SJue Wang
227eede2065SJue Wang run_ucna_injection(params);
228eede2065SJue Wang
229eede2065SJue Wang TEST_ASSERT(*params->p_i_ucna_rcvd == 1, "Only first UCNA get signaled.");
230eede2065SJue Wang TEST_ASSERT(*params->p_i_ucna_addr == FIRST_UCNA_ADDR,
231eede2065SJue Wang "Only first UCNA reported addr get recorded via interrupt.");
232eede2065SJue Wang TEST_ASSERT(*params->p_ucna_addr == FIRST_UCNA_ADDR,
233eede2065SJue Wang "First injected UCNAs should get exposed via registers.");
234eede2065SJue Wang TEST_ASSERT(*params->p_ucna_addr2 == SECOND_UCNA_ADDR,
235eede2065SJue Wang "Second injected UCNAs should get exposed via registers.");
236eede2065SJue Wang
237eede2065SJue Wang printf("Test successful.\n"
238eede2065SJue Wang "UCNA CMCI interrupts received: %ld\n"
239eede2065SJue Wang "Last UCNA address received via CMCI: %lx\n"
240eede2065SJue Wang "First UCNA address in vCPU thread: %lx\n"
241eede2065SJue Wang "Second UCNA address in vCPU thread: %lx\n",
242eede2065SJue Wang *params->p_i_ucna_rcvd, *params->p_i_ucna_addr,
243eede2065SJue Wang *params->p_ucna_addr, *params->p_ucna_addr2);
244eede2065SJue Wang }
245eede2065SJue Wang
setup_mce_cap(struct kvm_vcpu * vcpu,bool enable_cmci_p)246eede2065SJue Wang static void setup_mce_cap(struct kvm_vcpu *vcpu, bool enable_cmci_p)
247eede2065SJue Wang {
248eede2065SJue Wang uint64_t mcg_caps = MCG_CTL_P | MCG_SER_P | MCG_LMCE_P | KVM_MAX_MCE_BANKS;
249eede2065SJue Wang if (enable_cmci_p)
250eede2065SJue Wang mcg_caps |= MCG_CMCI_P;
251eede2065SJue Wang
252eede2065SJue Wang mcg_caps &= supported_mcg_caps | MCG_CAP_BANKS_MASK;
253eede2065SJue Wang vcpu_ioctl(vcpu, KVM_X86_SETUP_MCE, &mcg_caps);
254eede2065SJue Wang }
255eede2065SJue Wang
create_vcpu_with_mce_cap(struct kvm_vm * vm,uint32_t vcpuid,bool enable_cmci_p,void * guest_code)256eede2065SJue Wang static struct kvm_vcpu *create_vcpu_with_mce_cap(struct kvm_vm *vm, uint32_t vcpuid,
257eede2065SJue Wang bool enable_cmci_p, void *guest_code)
258eede2065SJue Wang {
259eede2065SJue Wang struct kvm_vcpu *vcpu = vm_vcpu_add(vm, vcpuid, guest_code);
260eede2065SJue Wang setup_mce_cap(vcpu, enable_cmci_p);
261eede2065SJue Wang return vcpu;
262eede2065SJue Wang }
263eede2065SJue Wang
main(int argc,char * argv[])264eede2065SJue Wang int main(int argc, char *argv[])
265eede2065SJue Wang {
266eede2065SJue Wang struct thread_params params;
267eede2065SJue Wang struct kvm_vm *vm;
268eede2065SJue Wang struct kvm_vcpu *ucna_vcpu;
269eede2065SJue Wang struct kvm_vcpu *cmcidis_vcpu;
270eede2065SJue Wang struct kvm_vcpu *cmci_vcpu;
271eede2065SJue Wang
272eede2065SJue Wang kvm_check_cap(KVM_CAP_MCE);
273eede2065SJue Wang
274eede2065SJue Wang vm = __vm_create(VM_MODE_DEFAULT, 3, 0);
275eede2065SJue Wang
276eede2065SJue Wang kvm_ioctl(vm->kvm_fd, KVM_X86_GET_MCE_CAP_SUPPORTED,
277eede2065SJue Wang &supported_mcg_caps);
278eede2065SJue Wang
279eede2065SJue Wang if (!(supported_mcg_caps & MCG_CMCI_P)) {
280eede2065SJue Wang print_skip("MCG_CMCI_P is not supported");
281eede2065SJue Wang exit(KSFT_SKIP);
282eede2065SJue Wang }
283eede2065SJue Wang
284eede2065SJue Wang ucna_vcpu = create_vcpu_with_mce_cap(vm, 0, true, ucna_injection_guest_code);
285eede2065SJue Wang cmcidis_vcpu = create_vcpu_with_mce_cap(vm, 1, false, cmci_disabled_guest_code);
286eede2065SJue Wang cmci_vcpu = create_vcpu_with_mce_cap(vm, 2, true, cmci_enabled_guest_code);
287eede2065SJue Wang
288eede2065SJue Wang vm_init_descriptor_tables(vm);
289eede2065SJue Wang vcpu_init_descriptor_tables(ucna_vcpu);
290eede2065SJue Wang vcpu_init_descriptor_tables(cmcidis_vcpu);
291eede2065SJue Wang vcpu_init_descriptor_tables(cmci_vcpu);
292eede2065SJue Wang vm_install_exception_handler(vm, CMCI_VECTOR, guest_cmci_handler);
293eede2065SJue Wang vm_install_exception_handler(vm, GP_VECTOR, guest_gp_handler);
294eede2065SJue Wang
295eede2065SJue Wang virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA);
296eede2065SJue Wang
297eede2065SJue Wang test_ucna_injection(ucna_vcpu, ¶ms);
298eede2065SJue Wang run_vcpu_expect_gp(cmcidis_vcpu);
299eede2065SJue Wang run_vcpu_expect_gp(cmci_vcpu);
300eede2065SJue Wang
301eede2065SJue Wang kvm_vm_free(vm);
302eede2065SJue Wang }
303