Home
last modified time | relevance | path

Searched +full:cs +full:- +full:1 (Results 1 – 25 of 1076) sorted by relevance

12345678910>>...44

/openbmc/qemu/semihosting/
H A Dsyscalls.c6 * SPDX-License-Identifier: GPL-2.0-or-later
25 static int validate_strlen(CPUState *cs, target_ulong str, target_ulong tlen) in validate_strlen() argument
27 CPUArchState *env G_GNUC_UNUSED = cpu_env(cs); in validate_strlen()
34 return -EFAULT; in validate_strlen()
37 return -ENAMETOOLONG; in validate_strlen()
39 return slen + 1; in validate_strlen()
42 return -ENAMETOOLONG; in validate_strlen()
44 if (get_user_u8(c, str + tlen - 1)) { in validate_strlen()
45 return -EFAULT; in validate_strlen()
48 return -EINVAL; in validate_strlen()
[all …]
H A Darm-compat-semi.c3 * semihosting syscalls design. This includes Arm and RISC-V processors
10 * Adapted for systems other than ARM, including RISC-V, by Keith Packard
27 * https://github.com/ARM-software/abi-aa/blob/main/semihosting/semihosting.rst
29 * RISC-V Semihosting is documented in:
30 * RISC-V Semihosting
31 * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
40 #include "semihosting/common-semi.h"
81 * anything else is implemented as exit(1) */
130 if (!mr->ram || mr->readonly) { in find_ram_cb()
134 if (size > info->ramsize) { in find_ram_cb()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c1 // SPDX-License-Identifier: GPL-2.0
46 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1,
59 * Args: freq - current sequence frequency
60 * dram_info - main struct
66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
70 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw()
71 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
76 if (reg & (1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)) { in ddr3_write_leveling_hw()
77 dpde_flag = 1; in ddr3_write_leveling_hw()
79 reg & ~(1 << REG_DUNIT_CTRL_LOW_DPDE_OFFS)); in ddr3_write_leveling_hw()
[all …]
H A Dddr3_read_leveling.c1 // SPDX-License-Identifier: GPL-2.0
44 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq,
48 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq,
56 * Args: dram_info - main struct
57 * freq - current sequence frequency
65 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_hw()
66 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw()
69 reg = 1 << REG_DRAM_TRAINING_RL_OFFS; in ddr3_read_leveling_hw()
73 /* Enable CS in the automatic process */ in ddr3_read_leveling_hw()
74 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
[all …]
/openbmc/qemu/hw/intc/
H A Darm_gicv3_redist.c17 static uint32_t mask_group(GICv3CPUState *cs, MemTxAttrs attrs) in mask_group() argument
19 /* Return a 32-bit mask which should be applied for this set of 32 in mask_group()
20 * interrupts; each bit is 1 if access is permitted by the in mask_group()
24 if (!attrs.secure && !(cs->gic->gicd_ctlr & GICD_CTLR_DS)) { in mask_group()
25 /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI */ in mask_group()
26 return cs->gicr_igroupr0; in mask_group()
31 static int gicr_ns_access(GICv3CPUState *cs, int irq) in gicr_ns_access() argument
35 return extract32(cs->gicr_nsacr, irq * 2, 2); in gicr_ns_access()
38 static void gicr_write_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs, in gicr_write_bitmap_reg() argument
42 val &= mask_group(cs, attrs); in gicr_write_bitmap_reg()
[all …]
H A Darm_gicv3_cpuif.c18 #include "qemu/main-loop.h"
24 #include "target/arm/cpu-features.h"
36 return env->gicv3state; in icc_cs_from_env()
50 static inline int icv_min_vbpr(GICv3CPUState *cs) in icv_min_vbpr() argument
52 return 7 - cs->vprebits; in icv_min_vbpr()
55 static inline int ich_num_aprs(GICv3CPUState *cs) in ich_num_aprs() argument
57 /* Return the number of virtual APR registers (1, 2, or 4) */ in ich_num_aprs()
58 int aprmax = 1 << (cs->vprebits - 5); in ich_num_aprs()
59 assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0])); in ich_num_aprs()
93 * * access if NS EL1 and HCR_EL2.FMO == 1: in icv_access()
[all …]
H A Darm_gicv3.c24 static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio, bool nmi) in irqbetter() argument
33 if (prio != cs->hppi.prio) { in irqbetter()
34 return prio < cs->hppi.prio; in irqbetter()
38 * The same priority IRQ with non-maskable property should signal to in irqbetter()
41 if (nmi != cs->hppi.nmi) { in irqbetter()
49 if (irq <= cs->hppi.irq) { in irqbetter()
59 * of 32), and return a 32-bit integer which has a bit set for each in gicd_int_pending()
63 * + the PENDING latch is set OR it is level triggered and the input is 1 in gicd_int_pending()
67 * Conveniently we can bulk-calculate this with bitwise operations. in gicd_int_pending()
70 uint32_t pending = *gic_bmp_ptr32(s->pending, irq); in gicd_int_pending()
[all …]
H A Darm_gicv3_common.c2 * ARM GICv3 support - common bits of emulated and KVM kernel model
27 #include "qemu/error-report.h"
30 #include "hw/qdev-properties.h"
33 #include "hw/arm/linux-boot-if.h"
37 static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) in gicv3_gicd_no_migration_shift_bug_post_load() argument
39 if (cs->gicd_no_migration_shift_bug) { in gicv3_gicd_no_migration_shift_bug_post_load()
50 memmove(cs->group, (uint8_t *)cs->group + GIC_INTERNAL / 8, in gicv3_gicd_no_migration_shift_bug_post_load()
51 sizeof(cs->group) - GIC_INTERNAL / 8); in gicv3_gicd_no_migration_shift_bug_post_load()
52 memmove(cs->grpmod, (uint8_t *)cs->grpmod + GIC_INTERNAL / 8, in gicv3_gicd_no_migration_shift_bug_post_load()
53 sizeof(cs->grpmod) - GIC_INTERNAL / 8); in gicv3_gicd_no_migration_shift_bug_post_load()
[all …]
/openbmc/qemu/target/i386/hvf/
H A Dx86hvf.c2 * Copyright (c) 2003-2008 Fabrice Bellard
35 void hvf_set_segment(CPUState *cs, struct vmx_segment *vmx_seg, in hvf_set_segment() argument
38 vmx_seg->sel = qseg->selector; in hvf_set_segment()
39 vmx_seg->base = qseg->base; in hvf_set_segment()
40 vmx_seg->limit = qseg->limit; in hvf_set_segment()
42 if (!qseg->selector && !x86_is_real(cs) && !is_tr) { in hvf_set_segment()
45 vmx_seg->ar = 1 << 16; in hvf_set_segment()
48 vmx_seg->ar = (qseg->flags >> DESC_TYPE_SHIFT) & 0xf; in hvf_set_segment()
49 vmx_seg->ar |= ((qseg->flags >> DESC_G_SHIFT) & 1) << 15; in hvf_set_segment()
50 vmx_seg->ar |= ((qseg->flags >> DESC_B_SHIFT) & 1) << 14; in hvf_set_segment()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dgen7_renderclear.c1 // SPDX-License-Identifier: MIT
12 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
48 * a shader on every HW thread, and clear the thread-local registers. in num_primitives()
52 return bv->max_threads; in num_primitives()
59 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
61 case 1: in batch_get_defaults()
62 bv->max_threads = 70; in batch_get_defaults()
65 bv->max_threads = 140; in batch_get_defaults()
68 bv->max_threads = 280; in batch_get_defaults()
71 bv->surface_height = 16 * 16; in batch_get_defaults()
[all …]
H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
20 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
22 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
23 * produced by non-pipelined state commands), software needs to first
24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
27 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
32 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
33 * BEFORE the pipe-control with a post-sync op and no write-cache
[all …]
H A Dgen8_engine_cs.c1 // SPDX-License-Identifier: MIT
16 u32 *cs, flags = 0; in gen8_emit_flush_rcs() local
42 if (GRAPHICS_VER(rq->i915) == 9) in gen8_emit_flush_rcs()
46 if (IS_KABYLAKE(rq->i915) && IS_GRAPHICS_STEP(rq->i915, 0, STEP_C0)) in gen8_emit_flush_rcs()
58 cs = intel_ring_begin(rq, len); in gen8_emit_flush_rcs()
59 if (IS_ERR(cs)) in gen8_emit_flush_rcs()
60 return PTR_ERR(cs); in gen8_emit_flush_rcs()
63 cs = gen8_emit_pipe_control(cs, 0, 0); in gen8_emit_flush_rcs()
66 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, in gen8_emit_flush_rcs()
69 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); in gen8_emit_flush_rcs()
[all …]
/openbmc/qemu/target/loongarch/kvm/
H A Dkvm.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 #include "qemu/error-report.h"
15 #include "qemu/main-loop.h"
21 #include "exec/address-spaces.h"
27 #include "cpu-csr.h"
37 static int kvm_get_stealtime(CPUState *cs) in kvm_get_stealtime() argument
39 CPULoongArchState *env = cpu_env(cs); in kvm_get_stealtime()
44 .addr = (uint64_t)&env->stealtime.guest_addr, in kvm_get_stealtime()
47 err = kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); in kvm_get_stealtime()
52 err = kvm_vcpu_ioctl(cs, KVM_GET_DEVICE_ATTR, attr); in kvm_get_stealtime()
[all …]
/openbmc/u-boot/board/freescale/corenet_ds/
H A Dp4080ds_ddr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
78 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
79 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
80 .cs[2].bnds = CONFIG_SYS_DDR_CS2_BNDS,
81 .cs[3].bnds = CONFIG_SYS_DDR_CS3_BNDS,
82 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
83 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
84 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
85 .cs[2].config = CONFIG_SYS_DDR_CS2_CONFIG,
[all …]
/openbmc/linux/drivers/memory/
H A Dstm32-fmc2-ebi.c1 // SPDX-License-Identifier: GPL-2.0
32 #define FMC2_BCR_MUXEN BIT(1)
101 FMC2_REG_BCR = 1,
148 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
172 const struct stm32_fmc2_prop *prop, int cs);
173 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
176 int cs, u32 setup);
181 int cs) in stm32_fmc2_ebi_check_mux() argument
186 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_mux()
193 return -EINVAL; in stm32_fmc2_ebi_check_mux()
[all …]
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
32 #include <linux/omap-gpmc.h>
36 #include <linux/platform_data/mtd-nand-omap2.h>
38 #define DEVICE_NAME "omap-gpmc"
80 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
96 * The first 1MB of GPMC address space is typically mapped to
138 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
139 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
[all …]
/openbmc/qemu/target/mips/
H A Dkvm.c8 * Copyright (C) 2012-2014 Imagination Technologies Ltd.
19 #include "qemu/error-report.h"
20 #include "qemu/main-loop.h"
42 unsigned long kvm_arch_vcpu_id(CPUState *cs) in kvm_arch_vcpu_id() argument
44 return cs->cpu_index; in kvm_arch_vcpu_id()
64 int kvm_arch_init_vcpu(CPUState *cs) in kvm_arch_init_vcpu() argument
66 CPUMIPSState *env = cpu_env(cs); in kvm_arch_init_vcpu()
69 qemu_add_vm_change_state_handler(kvm_mips_update_state, cs); in kvm_arch_init_vcpu()
71 if (kvm_mips_fpu_cap && env->CP0_Config1 & (1 << CP0C1_FP)) { in kvm_arch_init_vcpu()
72 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_FPU, 0, 0); in kvm_arch_init_vcpu()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
[all …]
/openbmc/linux/drivers/scsi/
H A Dmyrs.c1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
104 static void myrs_qcmd(struct myrs_hba *cs, struct myrs_cmdblk *cmd_blk) in myrs_qcmd() argument
106 void __iomem *base = cs->io_base; in myrs_qcmd()
107 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_qcmd()
[all …]
/openbmc/linux/kernel/time/
H A Dclocksource.c1 // SPDX-License-Identifier: GPL-2.0+
20 #include "tick-internal.h"
23 static noinline u64 cycles_to_nsec_safe(struct clocksource *cs, u64 start, u64 end) in cycles_to_nsec_safe() argument
25 u64 delta = clocksource_delta(end, start, cs->mask); in cycles_to_nsec_safe()
27 if (likely(delta < cs->max_cycles)) in cycles_to_nsec_safe()
28 return clocksource_cyc2ns(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
30 return mul_u64_u32_shr(delta, cs->mult, cs->shift); in cycles_to_nsec_safe()
34 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
45 * NSEC_PER_SEC == 1GHz and @from is the counter frequency. For clock
68 tmp >>=1; in clocks_calc_mult_shift()
[all …]
/openbmc/linux/include/linux/mfd/syscon/
H A Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
[all …]
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define TRAINING_TRIGGER_ENA 1
13 #define TRAINING_DONE_OFFS 1
15 #define TRAINING_DONE_DONE 1
20 #define TRAINING_RESULT_FAIL 1
118 #define CS_STRUCT_OFFS(cs) (CS_STRUCT_BASE + (cs) * 4) argument
121 #define CS_SIZE_OFFS(cs) (CS_SIZE_BASE + (cs) * 4) argument
124 #define CS_SIZE_HIGH_OFFS(cs) (CS_SIZE_HIGH_BASE + (cs)) argument
135 #define SDRAM_OP_CMD_CS_OFFS(cs) (SDRAM_OP_CMD_CS_BASE + (cs)) argument
165 #define CPU_INTERJECTION_ENA_SPLIT_DIS 1
[all …]
/openbmc/qemu/target/i386/
H A Dhelper.c21 #include "qapi/qapi-events-run-state.h"
23 #include "exec/exec-all.h"
32 #include "tcg/insn-start-words.h"
37 if ((env->cr[4] & CR4_OSXSAVE_MASK) in cpu_sync_avx_hflag()
38 && (env->xcr0 & (XSTATE_SSE_MASK | XSTATE_YMM_MASK)) in cpu_sync_avx_hflag()
40 env->hflags |= HF_AVX_EN_MASK; in cpu_sync_avx_hflag()
42 env->hflags &= ~HF_AVX_EN_MASK; in cpu_sync_avx_hflag()
48 uint32_t hflags = env->hflags; in cpu_sync_bndcs_hflags()
49 uint32_t hflags2 = env->hflags2; in cpu_sync_bndcs_hflags()
53 bndcsr = env->bndcs_regs.cfgu; in cpu_sync_bndcs_hflags()
[all …]
/openbmc/qemu/target/s390x/
H A Dgdbstub.c4 * Copyright (c) 2003-2005 Fabrice Bellard
23 #include "s390x-internal.h"
24 #include "exec/exec-all.h"
31 int s390_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) in s390_cpu_gdb_read_register() argument
33 CPUS390XState *env = cpu_env(cs); in s390_cpu_gdb_read_register()
39 return gdb_get_regl(mem_buf, env->psw.addr); in s390_cpu_gdb_read_register()
41 return gdb_get_regl(mem_buf, env->regs[n - S390_R0_REGNUM]); in s390_cpu_gdb_read_register()
46 int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) in s390_cpu_gdb_write_register() argument
48 CPUS390XState *env = cpu_env(cs); in s390_cpu_gdb_write_register()
53 s390_cpu_set_psw(env, tmpl, env->psw.addr); in s390_cpu_gdb_write_register()
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dm5307sim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
39 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
59 #define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
[all …]

12345678910>>...44