Lines Matching +full:cs +full:- +full:1
18 #include "qemu/main-loop.h"
24 #include "target/arm/cpu-features.h"
36 return env->gicv3state; in icc_cs_from_env()
50 static inline int icv_min_vbpr(GICv3CPUState *cs) in icv_min_vbpr() argument
52 return 7 - cs->vprebits; in icv_min_vbpr()
55 static inline int ich_num_aprs(GICv3CPUState *cs) in ich_num_aprs() argument
57 /* Return the number of virtual APR registers (1, 2, or 4) */ in ich_num_aprs()
58 int aprmax = 1 << (cs->vprebits - 5); in ich_num_aprs()
59 assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0])); in ich_num_aprs()
93 * * access if NS EL1 and HCR_EL2.FMO == 1: in icv_access()
95 * * access if NS EL1 and HCR_EL2.IMO == 1: in icv_access()
96 * all ICV regs with '1' in their name in icv_access()
97 * * access if NS EL1 and either IMO or FMO == 1: in icv_access()
103 return flagmatch && arm_current_el(env) == 1 in icv_access()
107 static int read_vbpr(GICv3CPUState *cs, int grp) in read_vbpr() argument
113 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in read_vbpr()
116 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT, in read_vbpr()
121 static void write_vbpr(GICv3CPUState *cs, int grp, int value) in write_vbpr() argument
126 int min = icv_min_vbpr(cs); in write_vbpr()
135 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in write_vbpr()
138 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT, in write_vbpr()
143 static uint32_t icv_fullprio_mask(GICv3CPUState *cs) in icv_fullprio_mask() argument
150 return (~0U << (8 - cs->vpribits)) & 0xff; in icv_fullprio_mask()
153 static int ich_highest_active_virt_prio(GICv3CPUState *cs) in ich_highest_active_virt_prio() argument
159 int aprmax = ich_num_aprs(cs); in ich_highest_active_virt_prio()
161 if (cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI) { in ich_highest_active_virt_prio()
166 uint32_t apr = cs->ich_apr[GICV3_G0][i] | in ich_highest_active_virt_prio()
167 cs->ich_apr[GICV3_G1NS][i]; in ich_highest_active_virt_prio()
172 return (i * 32 + ctz32(apr)) << (icv_min_vbpr(cs) + 1); in ich_highest_active_virt_prio()
178 static int hppvi_index(GICv3CPUState *cs) in hppvi_index() argument
183 * pseudocode. If no pending virtual interrupts, return -1. in hppvi_index()
190 ARMCPU *cpu = ARM_CPU(cs->cpu); in hppvi_index()
191 CPUARMState *env = &cpu->env; in hppvi_index()
192 int idx = -1; in hppvi_index()
201 if (!(cs->ich_vmcr_el2 & (ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1))) { in hppvi_index()
206 for (i = 0; i < cs->num_list_regs; i++) { in hppvi_index()
207 uint64_t lr = cs->ich_lr_el2[i]; in hppvi_index()
218 if (!(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { in hppvi_index()
222 if (!(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) { in hppvi_index()
240 * when we are in Non-Secure state. in hppvi_index()
242 if (cs->hppvlpi.prio < prio && !arm_is_secure(env)) { in hppvi_index()
243 if (cs->hppvlpi.grp == GICV3_G0) { in hppvi_index()
244 if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0) { in hppvi_index()
248 if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1) { in hppvi_index()
257 static uint32_t icv_gprio_mask(GICv3CPUState *cs, int group) in icv_gprio_mask() argument
263 * a BPR of 0 means the group priority bits are [7:1]; in icv_gprio_mask()
264 * a BPR of 1 means they are [7:2], and so on down to in icv_gprio_mask()
267 * a BPR of 0 is impossible (the minimum value is 1) in icv_gprio_mask()
268 * a BPR of 1 means the group priority bits are [7:1]; in icv_gprio_mask()
279 if (group == GICV3_G1NS && cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) { in icv_gprio_mask()
283 bpr = read_vbpr(cs, group); in icv_gprio_mask()
286 bpr--; in icv_gprio_mask()
289 return ~0U << (bpr + 1); in icv_gprio_mask()
292 static bool icv_hppi_can_preempt(GICv3CPUState *cs, uint64_t lr) in icv_hppi_can_preempt() argument
297 * Compare also icc_hppi_can_preempt() which is the non-virtual in icv_hppi_can_preempt()
304 if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) { in icv_hppi_can_preempt()
315 vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, in icv_hppi_can_preempt()
323 rprio = ich_highest_active_virt_prio(cs); in icv_hppi_can_preempt()
331 mask = icv_gprio_mask(cs, grp); in icv_hppi_can_preempt()
341 !(cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI)) { in icv_hppi_can_preempt()
348 static bool icv_hppvlpi_can_preempt(GICv3CPUState *cs) in icv_hppvlpi_can_preempt() argument
352 * We can assume we're Non-secure because hppvi_index() already in icv_hppvlpi_can_preempt()
357 if (!(cs->ich_hcr_el2 & ICH_HCR_EL2_EN)) { in icv_hppvlpi_can_preempt()
362 vpmr = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, in icv_hppvlpi_can_preempt()
365 if (cs->hppvlpi.prio >= vpmr) { in icv_hppvlpi_can_preempt()
370 rprio = ich_highest_active_virt_prio(cs); in icv_hppvlpi_can_preempt()
376 mask = icv_gprio_mask(cs, cs->hppvlpi.grp); in icv_hppvlpi_can_preempt()
382 if ((cs->hppvlpi.prio & mask) < (rprio & mask)) { in icv_hppvlpi_can_preempt()
389 static uint32_t eoi_maintenance_interrupt_state(GICv3CPUState *cs, in eoi_maintenance_interrupt_state() argument
394 * 1 if LR.State == 0 && LR.HW == 0 && LR.EOI == 1 in eoi_maintenance_interrupt_state()
404 for (i = 0; i < cs->num_list_regs; i++) { in eoi_maintenance_interrupt_state()
405 uint64_t lr = cs->ich_lr_el2[i]; in eoi_maintenance_interrupt_state()
409 value |= (1 << i); in eoi_maintenance_interrupt_state()
420 if (validcount < 2 && (cs->ich_hcr_el2 & ICH_HCR_EL2_UIE)) { in eoi_maintenance_interrupt_state()
423 if (!seenpending && (cs->ich_hcr_el2 & ICH_HCR_EL2_NPIE)) { in eoi_maintenance_interrupt_state()
433 static uint32_t maintenance_interrupt_state(GICv3CPUState *cs) in maintenance_interrupt_state() argument
441 eoi_maintenance_interrupt_state(cs, &value); in maintenance_interrupt_state()
443 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_LRENPIE) && in maintenance_interrupt_state()
444 (cs->ich_hcr_el2 & ICH_HCR_EL2_EOICOUNT_MASK)) { in maintenance_interrupt_state()
448 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP0EIE) && in maintenance_interrupt_state()
449 (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) { in maintenance_interrupt_state()
453 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP0DIE) && in maintenance_interrupt_state()
454 !(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { in maintenance_interrupt_state()
457 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP1EIE) && in maintenance_interrupt_state()
458 (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { in maintenance_interrupt_state()
462 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_VGRP1DIE) && in maintenance_interrupt_state()
463 !(cs->ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) { in maintenance_interrupt_state()
470 void gicv3_cpuif_virt_irq_fiq_update(GICv3CPUState *cs) in gicv3_cpuif_virt_irq_fiq_update() argument
486 idx = hppvi_index(cs); in gicv3_cpuif_virt_irq_fiq_update()
487 trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx, in gicv3_cpuif_virt_irq_fiq_update()
488 cs->hppvlpi.irq, cs->hppvlpi.grp, in gicv3_cpuif_virt_irq_fiq_update()
489 cs->hppvlpi.prio); in gicv3_cpuif_virt_irq_fiq_update()
491 if (icv_hppvlpi_can_preempt(cs)) { in gicv3_cpuif_virt_irq_fiq_update()
492 if (cs->hppvlpi.grp == GICV3_G0) { in gicv3_cpuif_virt_irq_fiq_update()
493 fiqlevel = 1; in gicv3_cpuif_virt_irq_fiq_update()
495 irqlevel = 1; in gicv3_cpuif_virt_irq_fiq_update()
499 uint64_t lr = cs->ich_lr_el2[idx]; in gicv3_cpuif_virt_irq_fiq_update()
501 if (icv_hppi_can_preempt(cs, lr)) { in gicv3_cpuif_virt_irq_fiq_update()
505 * non-maskable property. in gicv3_cpuif_virt_irq_fiq_update()
509 nmilevel = 1; in gicv3_cpuif_virt_irq_fiq_update()
511 irqlevel = 1; in gicv3_cpuif_virt_irq_fiq_update()
514 fiqlevel = 1; in gicv3_cpuif_virt_irq_fiq_update()
519 trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel); in gicv3_cpuif_virt_irq_fiq_update()
520 qemu_set_irq(cs->parent_vfiq, fiqlevel); in gicv3_cpuif_virt_irq_fiq_update()
521 qemu_set_irq(cs->parent_virq, irqlevel); in gicv3_cpuif_virt_irq_fiq_update()
522 qemu_set_irq(cs->parent_vnmi, nmilevel); in gicv3_cpuif_virt_irq_fiq_update()
525 static void gicv3_cpuif_virt_update(GICv3CPUState *cs) in gicv3_cpuif_virt_update() argument
534 * to the GIC as a per-CPU interrupt. This means that it in gicv3_cpuif_virt_update()
545 ARMCPU *cpu = ARM_CPU(cs->cpu); in gicv3_cpuif_virt_update()
548 gicv3_cpuif_virt_irq_fiq_update(cs); in gicv3_cpuif_virt_update()
550 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_EN) && in gicv3_cpuif_virt_update()
551 maintenance_interrupt_state(cs) != 0) { in gicv3_cpuif_virt_update()
552 maintlevel = 1; in gicv3_cpuif_virt_update()
555 trace_gicv3_cpuif_virt_set_maint_irq(gicv3_redist_affid(cs), maintlevel); in gicv3_cpuif_virt_update()
556 qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel); in gicv3_cpuif_virt_update()
561 GICv3CPUState *cs = icc_cs_from_env(env); in icv_ap_read() local
562 int regno = ri->opc2 & 3; in icv_ap_read()
563 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in icv_ap_read()
564 uint64_t value = cs->ich_apr[grp][regno]; in icv_ap_read()
566 trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icv_ap_read()
573 GICv3CPUState *cs = icc_cs_from_env(env); in icv_ap_write() local
574 int regno = ri->opc2 & 3; in icv_ap_write()
575 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in icv_ap_write()
577 trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icv_ap_write()
579 if (cs->nmi_support) { in icv_ap_write()
580 cs->ich_apr[grp][regno] = value & (0xFFFFFFFFU | ICV_AP1R_EL1_NMI); in icv_ap_write()
582 cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; in icv_ap_write()
585 gicv3_cpuif_virt_irq_fiq_update(cs); in icv_ap_write()
591 GICv3CPUState *cs = icc_cs_from_env(env); in icv_bpr_read() local
592 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS; in icv_bpr_read()
596 if (grp == GICV3_G1NS && (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) { in icv_bpr_read()
597 /* reads return bpr0 + 1 saturated to 7, writes ignored */ in icv_bpr_read()
602 bpr = read_vbpr(cs, grp); in icv_bpr_read()
609 trace_gicv3_icv_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr); in icv_bpr_read()
617 GICv3CPUState *cs = icc_cs_from_env(env); in icv_bpr_write() local
618 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS; in icv_bpr_write()
620 trace_gicv3_icv_bpr_write(ri->crm == 8 ? 0 : 1, in icv_bpr_write()
621 gicv3_redist_affid(cs), value); in icv_bpr_write()
623 if (grp == GICV3_G1NS && (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) { in icv_bpr_write()
624 /* reads return bpr0 + 1 saturated to 7, writes ignored */ in icv_bpr_write()
628 write_vbpr(cs, grp, value); in icv_bpr_write()
630 gicv3_cpuif_virt_irq_fiq_update(cs); in icv_bpr_write()
635 GICv3CPUState *cs = icc_cs_from_env(env); in icv_pmr_read() local
638 value = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, in icv_pmr_read()
641 trace_gicv3_icv_pmr_read(gicv3_redist_affid(cs), value); in icv_pmr_read()
648 GICv3CPUState *cs = icc_cs_from_env(env); in icv_pmr_write() local
650 trace_gicv3_icv_pmr_write(gicv3_redist_affid(cs), value); in icv_pmr_write()
652 value &= icv_fullprio_mask(cs); in icv_pmr_write()
654 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT, in icv_pmr_write()
657 gicv3_cpuif_virt_irq_fiq_update(cs); in icv_pmr_write()
662 GICv3CPUState *cs = icc_cs_from_env(env); in icv_igrpen_read() local
666 enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; in icv_igrpen_read()
667 value = extract64(cs->ich_vmcr_el2, enbit, 1); in icv_igrpen_read()
669 trace_gicv3_icv_igrpen_read(ri->opc2 & 1 ? 1 : 0, in icv_igrpen_read()
670 gicv3_redist_affid(cs), value); in icv_igrpen_read()
677 GICv3CPUState *cs = icc_cs_from_env(env); in icv_igrpen_write() local
680 trace_gicv3_icv_igrpen_write(ri->opc2 & 1 ? 1 : 0, in icv_igrpen_write()
681 gicv3_redist_affid(cs), value); in icv_igrpen_write()
683 enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; in icv_igrpen_write()
685 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, enbit, 1, value); in icv_igrpen_write()
686 gicv3_cpuif_virt_update(cs); in icv_igrpen_write()
691 GICv3CPUState *cs = icc_cs_from_env(env); in icv_ctlr_read() local
697 value = ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | in icv_ctlr_read()
698 ((cs->vpribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT); in icv_ctlr_read()
700 if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM) { in icv_ctlr_read()
704 if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) { in icv_ctlr_read()
708 trace_gicv3_icv_ctlr_read(gicv3_redist_affid(cs), value); in icv_ctlr_read()
715 GICv3CPUState *cs = icc_cs_from_env(env); in icv_ctlr_write() local
717 trace_gicv3_icv_ctlr_write(gicv3_redist_affid(cs), value); in icv_ctlr_write()
719 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VCBPR_SHIFT, in icv_ctlr_write()
720 1, value & ICC_CTLR_EL1_CBPR ? 1 : 0); in icv_ctlr_write()
721 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VEOIM_SHIFT, in icv_ctlr_write()
722 1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0); in icv_ctlr_write()
724 gicv3_cpuif_virt_irq_fiq_update(cs); in icv_ctlr_write()
729 GICv3CPUState *cs = icc_cs_from_env(env); in icv_rpr_read() local
730 uint64_t prio = ich_highest_active_virt_prio(cs); in icv_rpr_read()
732 if (cs->ich_apr[GICV3_G1NS][0] & ICV_AP1R_EL1_NMI) { in icv_rpr_read()
736 trace_gicv3_icv_rpr_read(gicv3_redist_affid(cs), prio); in icv_rpr_read()
742 GICv3CPUState *cs = icc_cs_from_env(env); in icv_hppir_read() local
743 int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; in icv_hppir_read()
744 int idx = hppvi_index(cs); in icv_hppir_read()
748 if (cs->hppvlpi.grp == grp) { in icv_hppir_read()
749 value = cs->hppvlpi.irq; in icv_hppir_read()
752 uint64_t lr = cs->ich_lr_el2[idx]; in icv_hppir_read()
760 trace_gicv3_icv_hppir_read(ri->crm == 8 ? 0 : 1, in icv_hppir_read()
761 gicv3_redist_affid(cs), value); in icv_hppir_read()
765 static void icv_activate_irq(GICv3CPUState *cs, int idx, int grp) in icv_activate_irq() argument
771 uint32_t mask = icv_gprio_mask(cs, grp); in icv_activate_irq()
772 int prio = ich_lr_prio(cs->ich_lr_el2[idx]) & mask; in icv_activate_irq()
773 bool nmi = cs->ich_lr_el2[idx] & ICH_LR_EL2_NMI; in icv_activate_irq()
774 int aprbit = prio >> (8 - cs->vprebits); in icv_activate_irq()
778 cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT; in icv_activate_irq()
779 cs->ich_lr_el2[idx] |= ICH_LR_EL2_STATE_ACTIVE_BIT; in icv_activate_irq()
782 cs->ich_apr[grp][regno] |= ICV_AP1R_EL1_NMI; in icv_activate_irq()
784 cs->ich_apr[grp][regno] |= (1U << regbit); in icv_activate_irq()
788 static void icv_activate_vlpi(GICv3CPUState *cs) in icv_activate_vlpi() argument
790 uint32_t mask = icv_gprio_mask(cs, cs->hppvlpi.grp); in icv_activate_vlpi()
791 int prio = cs->hppvlpi.prio & mask; in icv_activate_vlpi()
792 int aprbit = prio >> (8 - cs->vprebits); in icv_activate_vlpi()
796 cs->ich_apr[cs->hppvlpi.grp][regno] |= (1U << regbit); in icv_activate_vlpi()
797 gicv3_redist_vlpi_pending(cs, cs->hppvlpi.irq, 0); in icv_activate_vlpi()
802 GICv3CPUState *cs = icc_cs_from_env(env); in icv_iar_read() local
803 int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; in icv_iar_read()
804 int idx = hppvi_index(cs); in icv_iar_read()
809 if (cs->hppvlpi.grp == grp && icv_hppvlpi_can_preempt(cs)) { in icv_iar_read()
810 intid = cs->hppvlpi.irq; in icv_iar_read()
811 icv_activate_vlpi(cs); in icv_iar_read()
814 uint64_t lr = cs->ich_lr_el2[idx]; in icv_iar_read()
816 bool nmi = env->cp15.sctlr_el[el] & SCTLR_NMI && lr & ICH_LR_EL2_NMI; in icv_iar_read()
818 if (thisgrp == grp && icv_hppi_can_preempt(cs, lr)) { in icv_iar_read()
822 icv_activate_irq(cs, idx, grp); in icv_iar_read()
828 cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT; in icv_iar_read()
836 trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1, in icv_iar_read()
837 gicv3_redist_affid(cs), intid); in icv_iar_read()
839 gicv3_cpuif_virt_update(cs); in icv_iar_read()
846 GICv3CPUState *cs = icc_cs_from_env(env); in icv_nmiar1_read() local
847 int idx = hppvi_index(cs); in icv_nmiar1_read()
851 uint64_t lr = cs->ich_lr_el2[idx]; in icv_nmiar1_read()
854 if ((thisgrp == GICV3_G1NS) && icv_hppi_can_preempt(cs, lr)) { in icv_nmiar1_read()
858 icv_activate_irq(cs, idx, GICV3_G1NS); in icv_nmiar1_read()
864 cs->ich_lr_el2[idx] &= ~ICH_LR_EL2_STATE_PENDING_BIT; in icv_nmiar1_read()
873 trace_gicv3_icv_nmiar1_read(gicv3_redist_affid(cs), intid); in icv_nmiar1_read()
875 gicv3_cpuif_virt_update(cs); in icv_nmiar1_read()
880 static uint32_t icc_fullprio_mask(GICv3CPUState *cs) in icc_fullprio_mask() argument
888 return (~0U << (8 - cs->pribits)) & 0xff; in icc_fullprio_mask()
891 static inline int icc_min_bpr(GICv3CPUState *cs) in icc_min_bpr() argument
894 return 7 - cs->prebits; in icc_min_bpr()
897 static inline int icc_min_bpr_ns(GICv3CPUState *cs) in icc_min_bpr_ns() argument
899 return icc_min_bpr(cs) + 1; in icc_min_bpr_ns()
902 static inline int icc_num_aprs(GICv3CPUState *cs) in icc_num_aprs() argument
904 /* Return the number of APR registers (1, 2, or 4) */ in icc_num_aprs()
905 int aprmax = 1 << MAX(cs->prebits - 5, 0); in icc_num_aprs()
906 assert(aprmax <= ARRAY_SIZE(cs->icc_apr[0])); in icc_num_aprs()
910 static int icc_highest_active_prio(GICv3CPUState *cs) in icc_highest_active_prio() argument
917 if (cs->nmi_support) { in icc_highest_active_prio()
924 * prioritization of NMI vs non-NMI. in icc_highest_active_prio()
926 if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) { in icc_highest_active_prio()
929 if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { in icc_highest_active_prio()
930 return (cs->gic->gicd_ctlr & GICD_CTLR_DS) ? 0 : 0x80; in icc_highest_active_prio()
934 for (i = 0; i < icc_num_aprs(cs); i++) { in icc_highest_active_prio()
935 uint32_t apr = cs->icc_apr[GICV3_G0][i] | in icc_highest_active_prio()
936 cs->icc_apr[GICV3_G1][i] | cs->icc_apr[GICV3_G1NS][i]; in icc_highest_active_prio()
941 return (i * 32 + ctz32(apr)) << (icc_min_bpr(cs) + 1); in icc_highest_active_prio()
947 static uint32_t icc_gprio_mask(GICv3CPUState *cs, int group) in icc_gprio_mask() argument
952 * a BPR of 0 means the group priority bits are [7:1]; in icc_gprio_mask()
953 * a BPR of 1 means they are [7:2], and so on down to in icc_gprio_mask()
956 * a BPR of 0 is impossible (the minimum value is 1) in icc_gprio_mask()
957 * a BPR of 1 means the group priority bits are [7:1]; in icc_gprio_mask()
968 if ((group == GICV3_G1 && cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR) || in icc_gprio_mask()
970 cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { in icc_gprio_mask()
974 bpr = cs->icc_bpr[group] & 7; in icc_gprio_mask()
978 bpr--; in icc_gprio_mask()
981 return ~0U << (bpr + 1); in icc_gprio_mask()
984 static bool icc_no_enabled_hppi(GICv3CPUState *cs) in icc_no_enabled_hppi() argument
990 return cs->hppi.prio == 0xff || (cs->icc_igrpen[cs->hppi.grp] == 0); in icc_no_enabled_hppi()
993 static bool icc_hppi_can_preempt(GICv3CPUState *cs) in icc_hppi_can_preempt() argument
1000 ARMCPU *cpu = ARM_CPU(cs->cpu); in icc_hppi_can_preempt()
1001 CPUARMState *env = &cpu->env; in icc_hppi_can_preempt()
1003 if (icc_no_enabled_hppi(cs)) { in icc_hppi_can_preempt()
1007 if (cs->hppi.nmi) { in icc_hppi_can_preempt()
1008 if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && in icc_hppi_can_preempt()
1009 cs->hppi.grp == GICV3_G1NS) { in icc_hppi_can_preempt()
1010 if (cs->icc_pmr_el1 < 0x80) { in icc_hppi_can_preempt()
1013 if (arm_is_secure(env) && cs->icc_pmr_el1 == 0x80) { in icc_hppi_can_preempt()
1017 } else if (cs->hppi.prio >= cs->icc_pmr_el1) { in icc_hppi_can_preempt()
1022 rprio = icc_highest_active_prio(cs); in icc_hppi_can_preempt()
1028 mask = icc_gprio_mask(cs, cs->hppi.grp); in icc_hppi_can_preempt()
1033 if ((cs->hppi.prio & mask) < (rprio & mask)) { in icc_hppi_can_preempt()
1037 if (cs->hppi.nmi && (cs->hppi.prio & mask) == (rprio & mask)) { in icc_hppi_can_preempt()
1038 if (!(cs->icc_apr[cs->hppi.grp][0] & ICC_AP1R_EL1_NMI)) { in icc_hppi_can_preempt()
1046 void gicv3_cpuif_update(GICv3CPUState *cs) in gicv3_cpuif_update() argument
1052 ARMCPU *cpu = ARM_CPU(cs->cpu); in gicv3_cpuif_update()
1053 CPUARMState *env = &cpu->env; in gicv3_cpuif_update()
1057 trace_gicv3_cpuif_update(gicv3_redist_affid(cs), cs->hppi.irq, in gicv3_cpuif_update()
1058 cs->hppi.grp, cs->hppi.prio); in gicv3_cpuif_update()
1060 if (cs->hppi.grp == GICV3_G1 && !arm_feature(env, ARM_FEATURE_EL3)) { in gicv3_cpuif_update()
1061 /* If a Security-enabled GIC sends a G1S interrupt to a in gicv3_cpuif_update()
1062 * Security-disabled CPU, we must treat it as if it were G0. in gicv3_cpuif_update()
1064 cs->hppi.grp = GICV3_G0; in gicv3_cpuif_update()
1067 if (icc_hppi_can_preempt(cs)) { in gicv3_cpuif_update()
1073 switch (cs->hppi.grp) { in gicv3_cpuif_update()
1089 fiqlevel = 1; in gicv3_cpuif_update()
1090 } else if (cs->hppi.nmi) { in gicv3_cpuif_update()
1091 nmilevel = 1; in gicv3_cpuif_update()
1093 irqlevel = 1; in gicv3_cpuif_update()
1097 trace_gicv3_cpuif_set_irqs(gicv3_redist_affid(cs), fiqlevel, irqlevel); in gicv3_cpuif_update()
1099 qemu_set_irq(cs->parent_fiq, fiqlevel); in gicv3_cpuif_update()
1100 qemu_set_irq(cs->parent_irq, irqlevel); in gicv3_cpuif_update()
1101 qemu_set_irq(cs->parent_nmi, nmilevel); in gicv3_cpuif_update()
1106 GICv3CPUState *cs = icc_cs_from_env(env); in icc_pmr_read() local
1107 uint32_t value = cs->icc_pmr_el1; in icc_pmr_read()
1114 (env->cp15.scr_el3 & SCR_FIQ)) { in icc_pmr_read()
1122 value = (value << 1) & 0xff; in icc_pmr_read()
1126 trace_gicv3_icc_pmr_read(gicv3_redist_affid(cs), value); in icc_pmr_read()
1134 GICv3CPUState *cs = icc_cs_from_env(env); in icc_pmr_write() local
1140 trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value); in icc_pmr_write()
1143 (env->cp15.scr_el3 & SCR_FIQ)) { in icc_pmr_write()
1147 if (!(cs->icc_pmr_el1 & 0x80)) { in icc_pmr_write()
1151 value = (value >> 1) | 0x80; in icc_pmr_write()
1153 value &= icc_fullprio_mask(cs); in icc_pmr_write()
1154 cs->icc_pmr_el1 = value; in icc_pmr_write()
1155 gicv3_cpuif_update(cs); in icc_pmr_write()
1158 static void icc_activate_irq(GICv3CPUState *cs, int irq) in icc_activate_irq() argument
1163 uint32_t mask = icc_gprio_mask(cs, cs->hppi.grp); in icc_activate_irq()
1164 int prio = cs->hppi.prio & mask; in icc_activate_irq()
1165 int aprbit = prio >> (8 - cs->prebits); in icc_activate_irq()
1168 bool nmi = cs->hppi.nmi; in icc_activate_irq()
1171 cs->icc_apr[cs->hppi.grp][regno] |= ICC_AP1R_EL1_NMI; in icc_activate_irq()
1173 cs->icc_apr[cs->hppi.grp][regno] |= (1U << regbit); in icc_activate_irq()
1177 cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 1); in icc_activate_irq()
1178 cs->gicr_ipendr0 = deposit32(cs->gicr_ipendr0, irq, 1, 0); in icc_activate_irq()
1179 gicv3_redist_update(cs); in icc_activate_irq()
1181 gicv3_gicd_active_set(cs->gic, irq); in icc_activate_irq()
1182 gicv3_gicd_pending_clear(cs->gic, irq); in icc_activate_irq()
1183 gicv3_update(cs->gic, irq, 1); in icc_activate_irq()
1185 gicv3_redist_lpi_pending(cs, irq, 0); in icc_activate_irq()
1189 static uint64_t icc_hppir0_value(GICv3CPUState *cs, CPUARMState *env) in icc_hppir0_value() argument
1196 if (icc_no_enabled_hppi(cs)) { in icc_hppir0_value()
1205 irq_is_secure = (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && in icc_hppir0_value()
1206 (cs->hppi.grp != GICV3_G1NS)); in icc_hppir0_value()
1208 if (cs->hppi.grp != GICV3_G0 && !arm_is_el3_or_mon(env)) { in icc_hppir0_value()
1216 if (cs->hppi.grp != GICV3_G0) { in icc_hppir0_value()
1217 /* Indicate to EL3 that there's a Group 1 interrupt for the other in icc_hppir0_value()
1223 return cs->hppi.irq; in icc_hppir0_value()
1226 static uint64_t icc_hppir1_value(GICv3CPUState *cs, CPUARMState *env) in icc_hppir1_value() argument
1229 * for group 1. in icc_hppir1_value()
1233 if (icc_no_enabled_hppi(cs)) { in icc_hppir1_value()
1242 irq_is_secure = (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) && in icc_hppir1_value()
1243 (cs->hppi.grp != GICV3_G1NS)); in icc_hppir1_value()
1245 if (cs->hppi.grp == GICV3_G0) { in icc_hppir1_value()
1251 /* Secure interrupts not visible in Non-secure */ in icc_hppir1_value()
1255 /* Group 1 non-secure interrupts not visible in Secure EL1 */ in icc_hppir1_value()
1259 return cs->hppi.irq; in icc_hppir1_value()
1264 GICv3CPUState *cs = icc_cs_from_env(env); in icc_iar0_read() local
1271 if (!icc_hppi_can_preempt(cs)) { in icc_iar0_read()
1274 intid = icc_hppir0_value(cs, env); in icc_iar0_read()
1278 icc_activate_irq(cs, intid); in icc_iar0_read()
1281 trace_gicv3_icc_iar0_read(gicv3_redist_affid(cs), intid); in icc_iar0_read()
1287 GICv3CPUState *cs = icc_cs_from_env(env); in icc_iar1_read() local
1295 if (!icc_hppi_can_preempt(cs)) { in icc_iar1_read()
1298 intid = icc_hppir1_value(cs, env); in icc_iar1_read()
1302 if (cs->hppi.nmi && env->cp15.sctlr_el[el] & SCTLR_NMI) { in icc_iar1_read()
1305 icc_activate_irq(cs, intid); in icc_iar1_read()
1309 trace_gicv3_icc_iar1_read(gicv3_redist_affid(cs), intid); in icc_iar1_read()
1315 GICv3CPUState *cs = icc_cs_from_env(env); in icc_nmiar1_read() local
1322 if (!icc_hppi_can_preempt(cs)) { in icc_nmiar1_read()
1325 intid = icc_hppir1_value(cs, env); in icc_nmiar1_read()
1329 if (!cs->hppi.nmi) { in icc_nmiar1_read()
1332 icc_activate_irq(cs, intid); in icc_nmiar1_read()
1336 trace_gicv3_icc_nmiar1_read(gicv3_redist_affid(cs), intid); in icc_nmiar1_read()
1340 static void icc_drop_prio(GICv3CPUState *cs, int grp) in icc_drop_prio() argument
1360 for (i = 0; i < icc_num_aprs(cs); i++) { in icc_drop_prio()
1361 uint64_t *papr = &cs->icc_apr[grp][i]; in icc_drop_prio()
1367 if (i == 0 && cs->nmi_support && (*papr & ICC_AP1R_EL1_NMI)) { in icc_drop_prio()
1373 *papr &= *papr - 1; in icc_drop_prio()
1378 gicv3_cpuif_update(cs); in icc_drop_prio()
1381 static bool icc_eoi_split(CPUARMState *env, GICv3CPUState *cs) in icc_eoi_split() argument
1387 return cs->icc_ctlr_el3 & ICC_CTLR_EL3_EOIMODE_EL3; in icc_eoi_split()
1390 return cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1392 return cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE; in icc_eoi_split()
1396 static int icc_highest_active_group(GICv3CPUState *cs) in icc_highest_active_group() argument
1406 if (cs->nmi_support) { in icc_highest_active_group()
1407 if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) { in icc_highest_active_group()
1410 if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { in icc_highest_active_group()
1415 for (i = 0; i < ARRAY_SIZE(cs->icc_apr[0]); i++) { in icc_highest_active_group()
1416 int g0ctz = ctz32(cs->icc_apr[GICV3_G0][i]); in icc_highest_active_group()
1417 int g1ctz = ctz32(cs->icc_apr[GICV3_G1][i]); in icc_highest_active_group()
1418 int g1nsctz = ctz32(cs->icc_apr[GICV3_G1NS][i]); in icc_highest_active_group()
1430 /* No set active bits? UNPREDICTABLE; return -1 so the caller in icc_highest_active_group()
1433 return -1; in icc_highest_active_group()
1436 static void icc_deactivate_irq(GICv3CPUState *cs, int irq) in icc_deactivate_irq() argument
1439 cs->gicr_iactiver0 = deposit32(cs->gicr_iactiver0, irq, 1, 0); in icc_deactivate_irq()
1440 gicv3_redist_update(cs); in icc_deactivate_irq()
1442 gicv3_gicd_active_clear(cs->gic, irq); in icc_deactivate_irq()
1443 gicv3_update(cs->gic, irq, 1); in icc_deactivate_irq()
1447 static bool icv_eoi_split(CPUARMState *env, GICv3CPUState *cs) in icv_eoi_split() argument
1452 return cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM; in icv_eoi_split()
1455 static int icv_find_active(GICv3CPUState *cs, int irq) in icv_find_active() argument
1458 * of the corresponding list register, or -1 if there is no match. in icv_find_active()
1463 for (i = 0; i < cs->num_list_regs; i++) { in icv_find_active()
1464 uint64_t lr = cs->ich_lr_el2[i]; in icv_find_active()
1471 return -1; in icv_find_active()
1474 static void icv_deactivate_irq(GICv3CPUState *cs, int idx) in icv_deactivate_irq() argument
1477 uint64_t lr = cs->ich_lr_el2[idx]; in icv_deactivate_irq()
1484 icc_deactivate_irq(cs, pirq); in icv_deactivate_irq()
1488 /* Clear the 'active' part of the state, so ActivePending->Pending in icv_deactivate_irq()
1489 * and Active->Invalid. in icv_deactivate_irq()
1492 cs->ich_lr_el2[idx] = lr; in icv_deactivate_irq()
1495 static void icv_increment_eoicount(GICv3CPUState *cs) in icv_increment_eoicount() argument
1498 int eoicount = extract64(cs->ich_hcr_el2, ICH_HCR_EL2_EOICOUNT_SHIFT, in icv_increment_eoicount()
1501 cs->ich_hcr_el2 = deposit64(cs->ich_hcr_el2, ICH_HCR_EL2_EOICOUNT_SHIFT, in icv_increment_eoicount()
1502 ICH_HCR_EL2_EOICOUNT_LENGTH, eoicount + 1); in icv_increment_eoicount()
1505 static int icv_drop_prio(GICv3CPUState *cs, bool *nmi) in icv_drop_prio() argument
1509 * the same priority for both group 0 and group 1). in icv_drop_prio()
1516 int aprmax = ich_num_aprs(cs); in icv_drop_prio()
1519 uint64_t *papr0 = &cs->ich_apr[GICV3_G0][i]; in icv_drop_prio()
1520 uint64_t *papr1 = &cs->ich_apr[GICV3_G1NS][i]; in icv_drop_prio()
1527 if (i == 0 && cs->nmi_support && (*papr1 & ICV_AP1R_EL1_NMI)) { in icv_drop_prio()
1533 /* We can't just use the bit-twiddling hack icc_drop_prio() does in icv_drop_prio()
1541 *papr0 &= *papr0 - 1; in icv_drop_prio()
1542 return (apr0count + i * 32) << (icv_min_vbpr(cs) + 1); in icv_drop_prio()
1544 *papr1 &= *papr1 - 1; in icv_drop_prio()
1545 return (apr1count + i * 32) << (icv_min_vbpr(cs) + 1); in icv_drop_prio()
1555 GICv3CPUState *cs = icc_cs_from_env(env); in icv_dir_write() local
1559 trace_gicv3_icv_dir_write(gicv3_redist_affid(cs), value); in icv_dir_write()
1566 if (!icv_eoi_split(env, cs)) { in icv_dir_write()
1570 idx = icv_find_active(cs, irq); in icv_dir_write()
1576 icv_increment_eoicount(cs); in icv_dir_write()
1578 icv_deactivate_irq(cs, idx); in icv_dir_write()
1581 gicv3_cpuif_virt_update(cs); in icv_dir_write()
1588 GICv3CPUState *cs = icc_cs_from_env(env); in icv_eoir_write() local
1590 int grp = ri->crm == 8 ? GICV3_G0 : GICV3_G1NS; in icv_eoir_write()
1594 trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1, in icv_eoir_write()
1595 gicv3_redist_affid(cs), value); in icv_eoir_write()
1605 dropprio = icv_drop_prio(cs, &nmi); in icv_eoir_write()
1614 idx = icv_find_active(cs, irq); in icv_eoir_write()
1622 icv_increment_eoicount(cs); in icv_eoir_write()
1625 uint64_t lr = cs->ich_lr_el2[idx]; in icv_eoir_write()
1627 int lr_gprio = ich_lr_prio(lr) & icv_gprio_mask(cs, grp); in icv_eoir_write()
1631 if (!icv_eoi_split(env, cs) || irq >= GICV3_LPI_INTID_START) { in icv_eoir_write()
1637 icv_deactivate_irq(cs, idx); in icv_eoir_write()
1642 gicv3_cpuif_virt_update(cs); in icv_eoir_write()
1649 GICv3CPUState *cs = icc_cs_from_env(env); in icc_eoir_write() local
1652 bool is_eoir0 = ri->crm == 8; in icc_eoir_write()
1659 trace_gicv3_icc_eoir_write(is_eoir0 ? 0 : 1, in icc_eoir_write()
1660 gicv3_redist_affid(cs), value); in icc_eoir_write()
1662 if ((irq >= cs->gic->num_irq) && in icc_eoir_write()
1663 !(cs->gic->lpi_enable && (irq >= GICV3_LPI_INTID_START))) { in icc_eoir_write()
1665 * 1. If software writes the ID of a spurious interrupt [ie 1020-1023] in icc_eoir_write()
1667 * 2. If software writes the number of a non-existent interrupt in icc_eoir_write()
1675 grp = icc_highest_active_group(cs); in icc_eoir_write()
1681 if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) in icc_eoir_write()
1708 icc_drop_prio(cs, grp); in icc_eoir_write()
1710 if (!icc_eoi_split(env, cs)) { in icc_eoir_write()
1712 icc_deactivate_irq(cs, irq); in icc_eoir_write()
1718 GICv3CPUState *cs = icc_cs_from_env(env); in icc_hppir0_read() local
1725 value = icc_hppir0_value(cs, env); in icc_hppir0_read()
1726 trace_gicv3_icc_hppir0_read(gicv3_redist_affid(cs), value); in icc_hppir0_read()
1732 GICv3CPUState *cs = icc_cs_from_env(env); in icc_hppir1_read() local
1739 value = icc_hppir1_value(cs, env); in icc_hppir1_read()
1740 trace_gicv3_icc_hppir1_read(gicv3_redist_affid(cs), value); in icc_hppir1_read()
1746 GICv3CPUState *cs = icc_cs_from_env(env); in icc_bpr_read() local
1747 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1; in icc_bpr_read()
1760 (cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR)) { in icc_bpr_read()
1768 (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { in icc_bpr_read()
1769 /* reads return bpr0 + 1 sat to 7, writes ignored */ in icc_bpr_read()
1774 bpr = cs->icc_bpr[grp]; in icc_bpr_read()
1780 trace_gicv3_icc_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr); in icc_bpr_read()
1788 GICv3CPUState *cs = icc_cs_from_env(env); in icc_bpr_write() local
1789 int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1; in icc_bpr_write()
1797 trace_gicv3_icc_bpr_write(ri->crm == 8 ? 0 : 1, in icc_bpr_write()
1798 gicv3_redist_affid(cs), value); in icc_bpr_write()
1805 (cs->icc_ctlr_el1[GICV3_S] & ICC_CTLR_EL1_CBPR)) { in icc_bpr_write()
1813 (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR)) { in icc_bpr_write()
1814 /* reads return bpr0 + 1 sat to 7, writes ignored */ in icc_bpr_write()
1818 minval = (grp == GICV3_G1NS) ? icc_min_bpr_ns(cs) : icc_min_bpr(cs); in icc_bpr_write()
1823 cs->icc_bpr[grp] = value & 7; in icc_bpr_write()
1824 gicv3_cpuif_update(cs); in icc_bpr_write()
1829 GICv3CPUState *cs = icc_cs_from_env(env); in icc_ap_read() local
1832 int regno = ri->opc2 & 3; in icc_ap_read()
1833 int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0; in icc_ap_read()
1843 value = cs->icc_apr[grp][regno]; in icc_ap_read()
1845 trace_gicv3_icc_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icc_ap_read()
1852 GICv3CPUState *cs = icc_cs_from_env(env); in icc_ap_write() local
1854 int regno = ri->opc2 & 3; in icc_ap_write()
1855 int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0; in icc_ap_write()
1862 trace_gicv3_icc_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in icc_ap_write()
1868 /* It's not possible to claim that a Non-secure interrupt is active in icc_ap_write()
1869 * at a priority outside the Non-secure range (128..255), since this in icc_ap_write()
1877 if (cs->nmi_support) { in icc_ap_write()
1878 cs->icc_apr[grp][regno] = value & (0xFFFFFFFFU | ICC_AP1R_EL1_NMI); in icc_ap_write()
1880 cs->icc_apr[grp][regno] = value & 0xFFFFFFFFU; in icc_ap_write()
1882 gicv3_cpuif_update(cs); in icc_ap_write()
1889 GICv3CPUState *cs = icc_cs_from_env(env); in icc_dir_write() local
1899 trace_gicv3_icc_dir_write(gicv3_redist_affid(cs), value); in icc_dir_write()
1901 if (irq >= cs->gic->num_irq) { in icc_dir_write()
1906 if (!icc_eoi_split(env, cs)) { in icc_dir_write()
1910 int grp = gicv3_irq_group(cs->gic, cs, irq); in icc_dir_write()
1912 single_sec_state = cs->gic->gicd_ctlr & GICD_CTLR_DS; in icc_dir_write()
1920 route_fiq_to_el3 = env->cp15.scr_el3 & SCR_FIQ; in icc_dir_write()
1921 route_irq_to_el3 = env->cp15.scr_el3 & SCR_IRQ; in icc_dir_write()
1940 case 1: in icc_dir_write()
1965 icc_deactivate_irq(cs, irq); in icc_dir_write()
1970 GICv3CPUState *cs = icc_cs_from_env(env); in icc_rpr_read() local
1977 prio = icc_highest_active_prio(cs); in icc_rpr_read()
1980 !arm_is_secure(env) && (env->cp15.scr_el3 & SCR_FIQ)) { in icc_rpr_read()
1986 /* Non-idle priority: show the Non-secure view of it */ in icc_rpr_read()
1987 prio = (prio << 1) & 0xff; in icc_rpr_read()
1991 if (cs->nmi_support) { in icc_rpr_read()
1994 if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { in icc_rpr_read()
1998 if (cs->icc_apr[GICV3_G1NS][0] & ICC_AP1R_EL1_NMI) { in icc_rpr_read()
2001 if (cs->icc_apr[GICV3_G1][0] & ICC_AP1R_EL1_NMI) { in icc_rpr_read()
2007 trace_gicv3_icc_rpr_read(gicv3_redist_affid(cs), prio); in icc_rpr_read()
2011 static void icc_generate_sgi(CPUARMState *env, GICv3CPUState *cs, in icc_generate_sgi() argument
2014 GICv3State *s = cs->gic; in icc_generate_sgi()
2022 bool irm = extract64(value, 40, 1); in icc_generate_sgi()
2025 if (grp == GICV3_G1 && s->gicd_ctlr & GICD_CTLR_DS) { in icc_generate_sgi()
2026 /* If GICD_CTLR.DS == 1, the Distributor treats Secure Group 1 in icc_generate_sgi()
2033 trace_gicv3_icc_generate_sgi(gicv3_redist_affid(cs), irq, irm, in icc_generate_sgi()
2036 for (i = 0; i < s->num_cpu; i++) { in icc_generate_sgi()
2037 GICv3CPUState *ocs = &s->cpu[i]; in icc_generate_sgi()
2040 /* IRM == 1 : route to all CPUs except self */ in icc_generate_sgi()
2041 if (cs == ocs) { in icc_generate_sgi()
2050 if (ocs->gicr_typer >> 40 != aff) { in icc_generate_sgi()
2053 aff0 = extract64(ocs->gicr_typer, 32, 8); in icc_generate_sgi()
2054 if (aff0 > 15 || extract32(targetlist, aff0, 1) == 0) { in icc_generate_sgi()
2068 GICv3CPUState *cs = icc_cs_from_env(env); in icc_sgi0r_write() local
2071 icc_generate_sgi(env, cs, value, GICV3_G0, ns); in icc_sgi0r_write()
2077 /* Generate Group 1 SGI for the current Security state */ in icc_sgi1r_write()
2078 GICv3CPUState *cs = icc_cs_from_env(env); in icc_sgi1r_write() local
2083 icc_generate_sgi(env, cs, value, grp, ns); in icc_sgi1r_write()
2089 /* Generate Group 1 SGI for the Security state that is not in icc_asgi1r_write()
2092 GICv3CPUState *cs = icc_cs_from_env(env); in icc_asgi1r_write() local
2097 icc_generate_sgi(env, cs, value, grp, ns); in icc_asgi1r_write()
2102 GICv3CPUState *cs = icc_cs_from_env(env); in icc_igrpen_read() local
2103 int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0; in icc_igrpen_read()
2114 value = cs->icc_igrpen[grp]; in icc_igrpen_read()
2115 trace_gicv3_icc_igrpen_read(ri->opc2 & 1 ? 1 : 0, in icc_igrpen_read()
2116 gicv3_redist_affid(cs), value); in icc_igrpen_read()
2123 GICv3CPUState *cs = icc_cs_from_env(env); in icc_igrpen_write() local
2124 int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0; in icc_igrpen_write()
2131 trace_gicv3_icc_igrpen_write(ri->opc2 & 1 ? 1 : 0, in icc_igrpen_write()
2132 gicv3_redist_affid(cs), value); in icc_igrpen_write()
2138 cs->icc_igrpen[grp] = value & ICC_IGRPEN_ENABLE; in icc_igrpen_write()
2139 gicv3_cpuif_update(cs); in icc_igrpen_write()
2144 GICv3CPUState *cs = icc_cs_from_env(env); in icc_igrpen1_el3_read() local
2147 /* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */ in icc_igrpen1_el3_read()
2148 value = cs->icc_igrpen[GICV3_G1NS] | (cs->icc_igrpen[GICV3_G1] << 1); in icc_igrpen1_el3_read()
2149 trace_gicv3_icc_igrpen1_el3_read(gicv3_redist_affid(cs), value); in icc_igrpen1_el3_read()
2156 GICv3CPUState *cs = icc_cs_from_env(env); in icc_igrpen1_el3_write() local
2158 trace_gicv3_icc_igrpen1_el3_write(gicv3_redist_affid(cs), value); in icc_igrpen1_el3_write()
2160 /* IGRPEN1_EL3 bits 0 and 1 are r/w aliases into IGRPEN1_EL1 NS and S */ in icc_igrpen1_el3_write()
2161 cs->icc_igrpen[GICV3_G1NS] = extract32(value, 0, 1); in icc_igrpen1_el3_write()
2162 cs->icc_igrpen[GICV3_G1] = extract32(value, 1, 1); in icc_igrpen1_el3_write()
2163 gicv3_cpuif_update(cs); in icc_igrpen1_el3_write()
2168 GICv3CPUState *cs = icc_cs_from_env(env); in icc_ctlr_el1_read() local
2176 value = cs->icc_ctlr_el1[bank]; in icc_ctlr_el1_read()
2177 trace_gicv3_icc_ctlr_read(gicv3_redist_affid(cs), value); in icc_ctlr_el1_read()
2184 GICv3CPUState *cs = icc_cs_from_env(env); in icc_ctlr_el1_write() local
2193 trace_gicv3_icc_ctlr_write(gicv3_redist_affid(cs), value); in icc_ctlr_el1_write()
2196 * for us PMHE is RAZ/WI (we don't implement 1-of-N interrupts or in icc_ctlr_el1_write()
2197 * the asseciated priority-based routing of them); in icc_ctlr_el1_write()
2201 ((cs->gic->gicd_ctlr & GICD_CTLR_DS) == 0)) { in icc_ctlr_el1_write()
2207 cs->icc_ctlr_el1[bank] &= ~mask; in icc_ctlr_el1_write()
2208 cs->icc_ctlr_el1[bank] |= (value & mask); in icc_ctlr_el1_write()
2209 gicv3_cpuif_update(cs); in icc_ctlr_el1_write()
2215 GICv3CPUState *cs = icc_cs_from_env(env); in icc_ctlr_el3_read() local
2218 value = cs->icc_ctlr_el3; in icc_ctlr_el3_read()
2219 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
2222 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR) { in icc_ctlr_el3_read()
2225 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_EOIMODE) { in icc_ctlr_el3_read()
2228 if (cs->icc_ctlr_el1[GICV3_NS] & ICC_CTLR_EL1_CBPR) { in icc_ctlr_el3_read()
2232 trace_gicv3_icc_ctlr_el3_read(gicv3_redist_affid(cs), value); in icc_ctlr_el3_read()
2239 GICv3CPUState *cs = icc_cs_from_env(env); in icc_ctlr_el3_write() local
2242 trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value); in icc_ctlr_el3_write()
2245 cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); in icc_ctlr_el3_write()
2247 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el3_write()
2250 cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR; in icc_ctlr_el3_write()
2253 cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); in icc_ctlr_el3_write()
2255 cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE; in icc_ctlr_el3_write()
2258 cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_CBPR; in icc_ctlr_el3_write()
2264 cs->icc_ctlr_el3 &= ~mask; in icc_ctlr_el3_write()
2265 cs->icc_ctlr_el3 |= (value & mask); in icc_ctlr_el3_write()
2266 gicv3_cpuif_update(cs); in icc_ctlr_el3_write()
2273 GICv3CPUState *cs = icc_cs_from_env(env); in gicv3_irqfiq_access() local
2276 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TC) && in gicv3_irqfiq_access()
2277 el == 1 && !arm_is_secure_below_el3(env)) { in gicv3_irqfiq_access()
2282 if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) == (SCR_FIQ | SCR_IRQ)) { in gicv3_irqfiq_access()
2284 case 1: in gicv3_irqfiq_access()
2312 GICv3CPUState *cs = icc_cs_from_env(env); in gicv3_dir_access() local
2314 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TDIR) && in gicv3_dir_access()
2315 arm_current_el(env) == 1 && !arm_is_secure_below_el3(env)) { in gicv3_dir_access()
2326 if (arm_current_el(env) == 1 && in gicv3_sgi_access()
2339 GICv3CPUState *cs = icc_cs_from_env(env); in gicv3_fiq_access() local
2342 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TALL0) && in gicv3_fiq_access()
2343 el == 1 && !arm_is_secure_below_el3(env)) { in gicv3_fiq_access()
2348 if (env->cp15.scr_el3 & SCR_FIQ) { in gicv3_fiq_access()
2350 case 1: in gicv3_fiq_access()
2378 GICv3CPUState *cs = icc_cs_from_env(env); in gicv3_irq_access() local
2381 if ((cs->ich_hcr_el2 & ICH_HCR_EL2_TALL1) && in gicv3_irq_access()
2382 el == 1 && !arm_is_secure_below_el3(env)) { in gicv3_irq_access()
2387 if (env->cp15.scr_el3 & SCR_IRQ) { in gicv3_irq_access()
2389 case 1: in gicv3_irq_access()
2415 GICv3CPUState *cs = icc_cs_from_env(env); in icc_reset() local
2417 cs->icc_ctlr_el1[GICV3_S] = ICC_CTLR_EL1_A3V | in icc_reset()
2418 (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | in icc_reset()
2419 ((cs->pribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT); in icc_reset()
2420 cs->icc_ctlr_el1[GICV3_NS] = ICC_CTLR_EL1_A3V | in icc_reset()
2421 (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | in icc_reset()
2422 ((cs->pribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT); in icc_reset()
2423 cs->icc_pmr_el1 = 0; in icc_reset()
2424 cs->icc_bpr[GICV3_G0] = icc_min_bpr(cs); in icc_reset()
2425 cs->icc_bpr[GICV3_G1] = icc_min_bpr(cs); in icc_reset()
2426 cs->icc_bpr[GICV3_G1NS] = icc_min_bpr_ns(cs); in icc_reset()
2427 memset(cs->icc_apr, 0, sizeof(cs->icc_apr)); in icc_reset()
2428 memset(cs->icc_igrpen, 0, sizeof(cs->icc_igrpen)); in icc_reset()
2429 cs->icc_ctlr_el3 = ICC_CTLR_EL3_NDS | ICC_CTLR_EL3_A3V | in icc_reset()
2430 (1 << ICC_CTLR_EL3_IDBITS_SHIFT) | in icc_reset()
2431 ((cs->pribits - 1) << ICC_CTLR_EL3_PRIBITS_SHIFT); in icc_reset()
2433 memset(cs->ich_apr, 0, sizeof(cs->ich_apr)); in icc_reset()
2434 cs->ich_hcr_el2 = 0; in icc_reset()
2435 memset(cs->ich_lr_el2, 0, sizeof(cs->ich_lr_el2)); in icc_reset()
2436 cs->ich_vmcr_el2 = ICH_VMCR_EL2_VFIQEN | in icc_reset()
2437 ((icv_min_vbpr(cs) + 1) << ICH_VMCR_EL2_VBPR1_SHIFT) | in icc_reset()
2438 (icv_min_vbpr(cs) << ICH_VMCR_EL2_VBPR0_SHIFT); in icc_reset()
2461 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 1,
2495 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 1,
2525 .cp = 15, .opc1 = 1, .crm = 12,
2549 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 1,
2647 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 1,
2697 GICv3CPUState *cs = icc_cs_from_env(env); in ich_ap_read() local
2698 int regno = ri->opc2 & 3; in ich_ap_read()
2699 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in ich_ap_read()
2702 value = cs->ich_apr[grp][regno]; in ich_ap_read()
2703 trace_gicv3_ich_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in ich_ap_read()
2710 GICv3CPUState *cs = icc_cs_from_env(env); in ich_ap_write() local
2711 int regno = ri->opc2 & 3; in ich_ap_write()
2712 int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0; in ich_ap_write()
2714 trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value); in ich_ap_write()
2716 if (cs->nmi_support) { in ich_ap_write()
2717 cs->ich_apr[grp][regno] = value & (0xFFFFFFFFU | ICV_AP1R_EL1_NMI); in ich_ap_write()
2719 cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU; in ich_ap_write()
2721 gicv3_cpuif_virt_irq_fiq_update(cs); in ich_ap_write()
2726 GICv3CPUState *cs = icc_cs_from_env(env); in ich_hcr_read() local
2727 uint64_t value = cs->ich_hcr_el2; in ich_hcr_read()
2729 trace_gicv3_ich_hcr_read(gicv3_redist_affid(cs), value); in ich_hcr_read()
2736 GICv3CPUState *cs = icc_cs_from_env(env); in ich_hcr_write() local
2738 trace_gicv3_ich_hcr_write(gicv3_redist_affid(cs), value); in ich_hcr_write()
2746 cs->ich_hcr_el2 = value; in ich_hcr_write()
2747 gicv3_cpuif_virt_update(cs); in ich_hcr_write()
2752 GICv3CPUState *cs = icc_cs_from_env(env); in ich_vmcr_read() local
2753 uint64_t value = cs->ich_vmcr_el2; in ich_vmcr_read()
2755 trace_gicv3_ich_vmcr_read(gicv3_redist_affid(cs), value); in ich_vmcr_read()
2762 GICv3CPUState *cs = icc_cs_from_env(env); in ich_vmcr_write() local
2764 trace_gicv3_ich_vmcr_write(gicv3_redist_affid(cs), value); in ich_vmcr_write()
2771 cs->ich_vmcr_el2 = value; in ich_vmcr_write()
2775 write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0)); in ich_vmcr_write()
2776 write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1)); in ich_vmcr_write()
2778 gicv3_cpuif_virt_update(cs); in ich_vmcr_write()
2783 GICv3CPUState *cs = icc_cs_from_env(env); in ich_lr_read() local
2784 int regno = ri->opc2 | ((ri->crm & 1) << 3); in ich_lr_read()
2788 * 64-bit reads of the whole LR in ich_lr_read()
2789 * 32-bit reads of the low half of the LR in ich_lr_read()
2790 * 32-bit reads of the high half of the LR in ich_lr_read()
2792 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_read()
2793 if (ri->crm >= 14) { in ich_lr_read()
2794 value = extract64(cs->ich_lr_el2[regno], 32, 32); in ich_lr_read()
2795 trace_gicv3_ich_lrc_read(regno, gicv3_redist_affid(cs), value); in ich_lr_read()
2797 value = extract64(cs->ich_lr_el2[regno], 0, 32); in ich_lr_read()
2798 trace_gicv3_ich_lr32_read(regno, gicv3_redist_affid(cs), value); in ich_lr_read()
2801 value = cs->ich_lr_el2[regno]; in ich_lr_read()
2802 trace_gicv3_ich_lr_read(regno, gicv3_redist_affid(cs), value); in ich_lr_read()
2811 GICv3CPUState *cs = icc_cs_from_env(env); in ich_lr_write() local
2812 int regno = ri->opc2 | ((ri->crm & 1) << 3); in ich_lr_write()
2815 * 64-bit writes to the whole LR in ich_lr_write()
2816 * 32-bit writes to the low half of the LR in ich_lr_write()
2817 * 32-bit writes to the high half of the LR in ich_lr_write()
2819 if (ri->state == ARM_CP_STATE_AA32) { in ich_lr_write()
2820 if (ri->crm >= 14) { in ich_lr_write()
2821 trace_gicv3_ich_lrc_write(regno, gicv3_redist_affid(cs), value); in ich_lr_write()
2822 value = deposit64(cs->ich_lr_el2[regno], 32, 32, value); in ich_lr_write()
2824 trace_gicv3_ich_lr32_write(regno, gicv3_redist_affid(cs), value); in ich_lr_write()
2825 value = deposit64(cs->ich_lr_el2[regno], 0, 32, value); in ich_lr_write()
2828 trace_gicv3_ich_lr_write(regno, gicv3_redist_affid(cs), value); in ich_lr_write()
2832 if (cs->vpribits < 8) { in ich_lr_write()
2834 8 - cs->vpribits, 0); in ich_lr_write()
2838 if (!cs->nmi_support) { in ich_lr_write()
2842 cs->ich_lr_el2[regno] = value; in ich_lr_write()
2843 gicv3_cpuif_virt_update(cs); in ich_lr_write()
2848 GICv3CPUState *cs = icc_cs_from_env(env); in ich_vtr_read() local
2851 value = ((cs->num_list_regs - 1) << ICH_VTR_EL2_LISTREGS_SHIFT) in ich_vtr_read()
2853 | (1 << ICH_VTR_EL2_IDBITS_SHIFT) in ich_vtr_read()
2854 | ((cs->vprebits - 1) << ICH_VTR_EL2_PREBITS_SHIFT) in ich_vtr_read()
2855 | ((cs->vpribits - 1) << ICH_VTR_EL2_PRIBITS_SHIFT); in ich_vtr_read()
2857 if (cs->gic->revision < 4) { in ich_vtr_read()
2861 trace_gicv3_ich_vtr_read(gicv3_redist_affid(cs), value); in ich_vtr_read()
2867 GICv3CPUState *cs = icc_cs_from_env(env); in ich_misr_read() local
2868 uint64_t value = maintenance_interrupt_state(cs); in ich_misr_read()
2870 trace_gicv3_ich_misr_read(gicv3_redist_affid(cs), value); in ich_misr_read()
2876 GICv3CPUState *cs = icc_cs_from_env(env); in ich_eisr_read() local
2877 uint64_t value = eoi_maintenance_interrupt_state(cs, NULL); in ich_eisr_read()
2879 trace_gicv3_ich_eisr_read(gicv3_redist_affid(cs), value); in ich_eisr_read()
2885 GICv3CPUState *cs = icc_cs_from_env(env); in ich_elrsr_read() local
2889 for (i = 0; i < cs->num_list_regs; i++) { in ich_elrsr_read()
2890 uint64_t lr = cs->ich_lr_el2[i]; in ich_elrsr_read()
2894 value |= (1 << i); in ich_elrsr_read()
2898 trace_gicv3_ich_elrsr_read(gicv3_redist_affid(cs), value); in ich_elrsr_read()
2928 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 11, .opc2 = 1,
2963 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 8, .opc2 = 1,
2971 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 9, .opc2 = 1,
3017 GICv3CPUState *cs = opaque; in gicv3_cpuif_el_change_hook() local
3019 gicv3_cpuif_update(cs); in gicv3_cpuif_el_change_hook()
3025 gicv3_cpuif_virt_irq_fiq_update(cs); in gicv3_cpuif_el_change_hook()
3035 for (i = 0; i < s->num_cpu; i++) { in gicv3_init_cpuif()
3037 GICv3CPUState *cs = &s->cpu[i]; in gicv3_init_cpuif() local
3043 * cpu->gic_num_lrs in gicv3_init_cpuif()
3044 * cpu->gic_vpribits in gicv3_init_cpuif()
3045 * cpu->gic_vprebits in gicv3_init_cpuif()
3046 * cpu->gic_pribits in gicv3_init_cpuif()
3051 * it might be with code translated by CPU 0 but run by CPU 1, in in gicv3_init_cpuif()
3053 * So instead we define the regs with no ri->opaque info, and in gicv3_init_cpuif()
3065 * that is a property of the GIC device in s->nmi_support; in gicv3_init_cpuif()
3066 * cs->nmi_support indicates the CPU interface's support. in gicv3_init_cpuif()
3069 cs->nmi_support = true; in gicv3_init_cpuif()
3079 if (s->force_8bit_prio) { in gicv3_init_cpuif()
3080 cs->pribits = 8; in gicv3_init_cpuif()
3082 cs->pribits = cpu->gic_pribits ?: 5; in gicv3_init_cpuif()
3095 cs->prebits = cs->pribits; in gicv3_init_cpuif()
3096 if (cs->prebits == 8) { in gicv3_init_cpuif()
3097 cs->prebits--; in gicv3_init_cpuif()
3103 g_assert(cs->pribits >= 4 && cs->pribits <= 8); in gicv3_init_cpuif()
3107 * for ICC_AP*R{1,2,3}_EL1 if the prebits value requires them. in gicv3_init_cpuif()
3109 if (cs->prebits >= 6) { in gicv3_init_cpuif()
3112 if (cs->prebits == 7) { in gicv3_init_cpuif()
3116 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { in gicv3_init_cpuif()
3119 cs->num_list_regs = cpu->gic_num_lrs ?: 4; in gicv3_init_cpuif()
3120 cs->vpribits = cpu->gic_vpribits ?: 5; in gicv3_init_cpuif()
3121 cs->vprebits = cpu->gic_vprebits ?: 5; in gicv3_init_cpuif()
3127 g_assert(cs->vprebits <= cs->vpribits); in gicv3_init_cpuif()
3128 g_assert(cs->vprebits >= 5 && cs->vprebits <= 7); in gicv3_init_cpuif()
3129 g_assert(cs->vpribits >= 5 && cs->vpribits <= 8); in gicv3_init_cpuif()
3133 for (j = 0; j < cs->num_list_regs; j++) { in gicv3_init_cpuif()
3134 /* Note that the AArch64 LRs are 64-bit; the AArch32 LRs in gicv3_init_cpuif()
3159 if (cs->vprebits >= 6) { in gicv3_init_cpuif()
3162 if (cs->vprebits == 7) { in gicv3_init_cpuif()
3170 * the non-TCG case this is OK, as EL2 and EL3 can't exist. in gicv3_init_cpuif()
3172 arm_register_el_change_hook(cpu, gicv3_cpuif_el_change_hook, cs); in gicv3_init_cpuif()
3174 assert(!arm_feature(&cpu->env, ARM_FEATURE_EL2)); in gicv3_init_cpuif()
3175 assert(!arm_feature(&cpu->env, ARM_FEATURE_EL3)); in gicv3_init_cpuif()