Lines Matching +full:cs +full:- +full:1
21 #include "qapi/qapi-events-run-state.h"
23 #include "exec/exec-all.h"
32 #include "tcg/insn-start-words.h"
37 if ((env->cr[4] & CR4_OSXSAVE_MASK) in cpu_sync_avx_hflag()
38 && (env->xcr0 & (XSTATE_SSE_MASK | XSTATE_YMM_MASK)) in cpu_sync_avx_hflag()
40 env->hflags |= HF_AVX_EN_MASK; in cpu_sync_avx_hflag()
42 env->hflags &= ~HF_AVX_EN_MASK; in cpu_sync_avx_hflag()
48 uint32_t hflags = env->hflags; in cpu_sync_bndcs_hflags()
49 uint32_t hflags2 = env->hflags2; in cpu_sync_bndcs_hflags()
53 bndcsr = env->bndcs_regs.cfgu; in cpu_sync_bndcs_hflags()
55 bndcsr = env->msr_bndcfgs; in cpu_sync_bndcs_hflags()
58 if ((env->cr[4] & CR4_OSXSAVE_MASK) in cpu_sync_bndcs_hflags()
59 && (env->xcr0 & XSTATE_BNDCSR_MASK) in cpu_sync_bndcs_hflags()
72 env->hflags = hflags; in cpu_sync_bndcs_hflags()
73 env->hflags2 = hflags2; in cpu_sync_bndcs_hflags()
78 int cpuver = env->cpuid_version; in cpu_x86_version()
100 return 1; in cpu_x86_support_mca_broadcast()
112 CPUX86State *env = &cpu->env; in x86_cpu_set_a20()
115 if (a20_state != ((env->a20_mask >> 20) & 1)) { in x86_cpu_set_a20()
116 CPUState *cs = CPU(cpu); in x86_cpu_set_a20() local
121 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); in x86_cpu_set_a20()
125 tlb_flush(cs); in x86_cpu_set_a20()
126 env->a20_mask = ~(1 << 20) | (a20_state << 20); in x86_cpu_set_a20()
137 (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) { in cpu_x86_update_cr0()
142 if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) && in cpu_x86_update_cr0()
143 (env->efer & MSR_EFER_LME)) { in cpu_x86_update_cr0()
146 if (!(env->cr[4] & CR4_PAE_MASK)) in cpu_x86_update_cr0()
148 env->efer |= MSR_EFER_LMA; in cpu_x86_update_cr0()
149 env->hflags |= HF_LMA_MASK; in cpu_x86_update_cr0()
150 } else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) && in cpu_x86_update_cr0()
151 (env->efer & MSR_EFER_LMA)) { in cpu_x86_update_cr0()
153 env->efer &= ~MSR_EFER_LMA; in cpu_x86_update_cr0()
154 env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK); in cpu_x86_update_cr0()
155 env->eip &= 0xffffffff; in cpu_x86_update_cr0()
158 env->cr[0] = new_cr0 | CR0_ET_MASK; in cpu_x86_update_cr0()
161 pe_state = (env->cr[0] & CR0_PE_MASK); in cpu_x86_update_cr0()
162 env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT); in cpu_x86_update_cr0()
164 env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT); in cpu_x86_update_cr0()
166 env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) | in cpu_x86_update_cr0()
167 ((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)); in cpu_x86_update_cr0()
174 env->cr[3] = new_cr3; in cpu_x86_update_cr3()
175 if (env->cr[0] & CR0_PG_MASK) { in cpu_x86_update_cr3()
187 printf("CR4 update: %08x -> %08x\n", (uint32_t)env->cr[4], new_cr4); in cpu_x86_update_cr4()
189 if ((new_cr4 ^ env->cr[4]) & in cpu_x86_update_cr4()
196 hflags = env->hflags & ~(HF_OSFXSR_MASK | HF_SMAP_MASK | HF_UMIP_MASK); in cpu_x86_update_cr4()
199 if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) { in cpu_x86_update_cr4()
206 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) { in cpu_x86_update_cr4()
212 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) { in cpu_x86_update_cr4()
219 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) { in cpu_x86_update_cr4()
222 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { in cpu_x86_update_cr4()
226 if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_LAM)) { in cpu_x86_update_cr4()
230 env->cr[4] = new_cr4; in cpu_x86_update_cr4()
231 env->hflags = hflags; in cpu_x86_update_cr4()
238 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, in x86_cpu_get_phys_page_attrs_debug() argument
241 X86CPU *cpu = X86_CPU(cs); in x86_cpu_get_phys_page_attrs_debug()
242 CPUX86State *env = &cpu->env; in x86_cpu_get_phys_page_attrs_debug()
252 if (!(env->cr[0] & CR0_PG_MASK)) { in x86_cpu_get_phys_page_attrs_debug()
255 } else if (env->cr[4] & CR4_PAE_MASK) { in x86_cpu_get_phys_page_attrs_debug()
260 if (env->hflags & HF_LMA_MASK) { in x86_cpu_get_phys_page_attrs_debug()
261 bool la57 = env->cr[4] & CR4_LA57_MASK; in x86_cpu_get_phys_page_attrs_debug()
268 if (sext != 0 && sext != -1) { in x86_cpu_get_phys_page_attrs_debug()
269 return -1; in x86_cpu_get_phys_page_attrs_debug()
273 pml5e_addr = ((env->cr[3] & ~0xfff) + in x86_cpu_get_phys_page_attrs_debug()
275 pml5e = x86_ldq_phys(cs, pml5e_addr); in x86_cpu_get_phys_page_attrs_debug()
277 return -1; in x86_cpu_get_phys_page_attrs_debug()
280 pml5e = env->cr[3]; in x86_cpu_get_phys_page_attrs_debug()
285 pml4e = x86_ldq_phys(cs, pml4e_addr); in x86_cpu_get_phys_page_attrs_debug()
287 return -1; in x86_cpu_get_phys_page_attrs_debug()
291 pdpe = x86_ldq_phys(cs, pdpe_addr); in x86_cpu_get_phys_page_attrs_debug()
293 return -1; in x86_cpu_get_phys_page_attrs_debug()
304 pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) & in x86_cpu_get_phys_page_attrs_debug()
306 pdpe = x86_ldq_phys(cs, pdpe_addr); in x86_cpu_get_phys_page_attrs_debug()
308 return -1; in x86_cpu_get_phys_page_attrs_debug()
313 pde = x86_ldq_phys(cs, pde_addr); in x86_cpu_get_phys_page_attrs_debug()
315 return -1; in x86_cpu_get_phys_page_attrs_debug()
326 pte = x86_ldq_phys(cs, pte_addr); in x86_cpu_get_phys_page_attrs_debug()
329 return -1; in x86_cpu_get_phys_page_attrs_debug()
335 pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask; in x86_cpu_get_phys_page_attrs_debug()
336 pde = x86_ldl_phys(cs, pde_addr); in x86_cpu_get_phys_page_attrs_debug()
338 return -1; in x86_cpu_get_phys_page_attrs_debug()
339 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { in x86_cpu_get_phys_page_attrs_debug()
340 pte = pde | ((pde & 0x1fe000LL) << (32 - 13)); in x86_cpu_get_phys_page_attrs_debug()
345 pte = x86_ldl_phys(cs, pte_addr); in x86_cpu_get_phys_page_attrs_debug()
347 return -1; in x86_cpu_get_phys_page_attrs_debug()
357 pte &= PG_ADDRESS_MASK & ~(page_size - 1); in x86_cpu_get_phys_page_attrs_debug()
358 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1); in x86_cpu_get_phys_page_attrs_debug()
381 static void do_inject_x86_mce(CPUState *cs, run_on_cpu_data data) in do_inject_x86_mce() argument
384 X86CPU *cpu = X86_CPU(cs); in do_inject_x86_mce()
385 CPUX86State *cenv = &cpu->env; in do_inject_x86_mce()
386 uint64_t *banks = cenv->mce_banks + 4 * params->bank; in do_inject_x86_mce()
390 bool ar = !!(params->status & MCI_STATUS_AR); in do_inject_x86_mce()
392 cpu_synchronize_state(cs); in do_inject_x86_mce()
393 recursive = !!(cenv->mcg_status & MCG_STATUS_MCIP); in do_inject_x86_mce()
399 if (!(params->flags & MCE_INJECT_UNCOND_AO) && !ar && recursive) { in do_inject_x86_mce()
404 if (params->status & MCI_STATUS_UC) { in do_inject_x86_mce()
406 * if MSR_MCG_CTL is not all 1s, the uncorrected error in do_inject_x86_mce()
409 if ((cenv->mcg_cap & MCG_CTL_P) && cenv->mcg_ctl != ~(uint64_t)0) { in do_inject_x86_mce()
410 monitor_printf(params->mon, in do_inject_x86_mce()
412 cs->cpu_index); in do_inject_x86_mce()
417 * if MSR_MCi_CTL is not all 1s, the uncorrected error in do_inject_x86_mce()
421 monitor_printf(params->mon, in do_inject_x86_mce()
424 cs->cpu_index, params->bank); in do_inject_x86_mce()
428 if (!(cenv->cr[4] & CR4_MCE_MASK)) { in do_inject_x86_mce()
431 "raising triple fault", cs->cpu_index); in do_inject_x86_mce()
435 "raising triple fault", cs->cpu_index); in do_inject_x86_mce()
441 monitor_printf(params->mon, "%s", msg); in do_inject_x86_mce()
447 if (banks[1] & MCI_STATUS_VAL) { in do_inject_x86_mce()
448 params->status |= MCI_STATUS_OVER; in do_inject_x86_mce()
450 banks[2] = params->addr; in do_inject_x86_mce()
451 banks[3] = params->misc; in do_inject_x86_mce()
452 cenv->mcg_status = params->mcg_status; in do_inject_x86_mce()
453 banks[1] = params->status; in do_inject_x86_mce()
454 cpu_interrupt(cs, CPU_INTERRUPT_MCE); in do_inject_x86_mce()
455 } else if (!(banks[1] & MCI_STATUS_VAL) in do_inject_x86_mce()
456 || !(banks[1] & MCI_STATUS_UC)) { in do_inject_x86_mce()
457 if (banks[1] & MCI_STATUS_VAL) { in do_inject_x86_mce()
458 params->status |= MCI_STATUS_OVER; in do_inject_x86_mce()
460 banks[2] = params->addr; in do_inject_x86_mce()
461 banks[3] = params->misc; in do_inject_x86_mce()
462 banks[1] = params->status; in do_inject_x86_mce()
464 banks[1] |= MCI_STATUS_OVER; in do_inject_x86_mce()
474 CPUState *cs = CPU(cpu); in cpu_x86_inject_mce() local
475 CPUX86State *cenv = &cpu->env; in cpu_x86_inject_mce()
485 unsigned bank_num = cenv->mcg_cap & 0xff; in cpu_x86_inject_mce()
487 if (!cenv->mcg_cap) { in cpu_x86_inject_mce()
505 run_on_cpu(cs, do_inject_x86_mce, RUN_ON_CPU_HOST_PTR(¶ms)); in cpu_x86_inject_mce()
509 params.bank = 1; in cpu_x86_inject_mce()
515 if (other_cs == cs) { in cpu_x86_inject_mce()
527 CPUState *cs = env_cpu(env); in get_memio_eip() local
529 if (!cpu_unwind_state_data(cs, cs->mem_io_pc, data)) { in get_memio_eip()
530 return env->eip; in get_memio_eip()
534 if (tcg_cflags_has(cs, CF_PCREL)) { in get_memio_eip()
535 return (env->eip & TARGET_PAGE_MASK) | data[0]; in get_memio_eip()
537 return data[0] - env->segs[R_CS].base; in get_memio_eip()
547 CPUState *cs = env_cpu(env); in cpu_report_tpr_access() local
550 env->tpr_access_type = access; in cpu_report_tpr_access()
552 cpu_interrupt(cs, CPU_INTERRUPT_TPR); in cpu_report_tpr_access()
556 apic_handle_tpr_access_report(cpu->apic_state, eip, access); in cpu_report_tpr_access()
565 CPUState *cs = env_cpu(env); in cpu_x86_get_descr_debug() local
572 dt = &env->ldt; in cpu_x86_get_descr_debug()
574 dt = &env->gdt; in cpu_x86_get_descr_debug()
576 ptr = dt->base + index; in cpu_x86_get_descr_debug()
577 if ((index + 7) > dt->limit in cpu_x86_get_descr_debug()
578 || cpu_memory_rw_debug(cs, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0 in cpu_x86_get_descr_debug()
579 || cpu_memory_rw_debug(cs, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0) in cpu_x86_get_descr_debug()
588 return 1; in cpu_x86_get_descr_debug()
594 CPUState *cs = CPU(cpu); in do_cpu_init() local
595 CPUX86State *env = &cpu->env; in do_cpu_init()
596 CPUX86State *save = g_new(CPUX86State, 1); in do_cpu_init()
597 int sipi = cs->interrupt_request & CPU_INTERRUPT_SIPI; in do_cpu_init()
601 cpu_reset(cs); in do_cpu_init()
602 cs->interrupt_request = sipi; in do_cpu_init()
603 memcpy(&env->start_init_save, &save->start_init_save, in do_cpu_init()
604 offsetof(CPUX86State, end_init_save) - in do_cpu_init()
611 apic_init_reset(cpu->apic_state); in do_cpu_init()
619 apic_sipi(cpu->apic_state); in do_cpu_sipi()
624 env->efer = val; in cpu_load_efer()
625 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); in cpu_load_efer()
626 if (env->efer & MSR_EFER_LMA) { in cpu_load_efer()
627 env->hflags |= HF_LMA_MASK; in cpu_load_efer()
629 if (env->efer & MSR_EFER_SVME) { in cpu_load_efer()
630 env->hflags |= HF_SVME_MASK; in cpu_load_efer()
634 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr) in x86_ldub_phys() argument
636 X86CPU *cpu = X86_CPU(cs); in x86_ldub_phys()
637 CPUX86State *env = &cpu->env; in x86_ldub_phys()
639 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_ldub_phys()
644 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr) in x86_lduw_phys() argument
646 X86CPU *cpu = X86_CPU(cs); in x86_lduw_phys()
647 CPUX86State *env = &cpu->env; in x86_lduw_phys()
649 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_lduw_phys()
654 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr) in x86_ldl_phys() argument
656 X86CPU *cpu = X86_CPU(cs); in x86_ldl_phys()
657 CPUX86State *env = &cpu->env; in x86_ldl_phys()
659 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_ldl_phys()
664 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr) in x86_ldq_phys() argument
666 X86CPU *cpu = X86_CPU(cs); in x86_ldq_phys()
667 CPUX86State *env = &cpu->env; in x86_ldq_phys()
669 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_ldq_phys()
674 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val) in x86_stb_phys() argument
676 X86CPU *cpu = X86_CPU(cs); in x86_stb_phys()
677 CPUX86State *env = &cpu->env; in x86_stb_phys()
679 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_stb_phys()
684 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val) in x86_stl_phys_notdirty() argument
686 X86CPU *cpu = X86_CPU(cs); in x86_stl_phys_notdirty()
687 CPUX86State *env = &cpu->env; in x86_stl_phys_notdirty()
689 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_stl_phys_notdirty()
694 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val) in x86_stw_phys() argument
696 X86CPU *cpu = X86_CPU(cs); in x86_stw_phys()
697 CPUX86State *env = &cpu->env; in x86_stw_phys()
699 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_stw_phys()
704 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val) in x86_stl_phys() argument
706 X86CPU *cpu = X86_CPU(cs); in x86_stl_phys()
707 CPUX86State *env = &cpu->env; in x86_stl_phys()
709 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_stl_phys()
714 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val) in x86_stq_phys() argument
716 X86CPU *cpu = X86_CPU(cs); in x86_stq_phys()
717 CPUX86State *env = &cpu->env; in x86_stq_phys()
719 AddressSpace *as = cpu_addressspace(cs, attrs); in x86_stq_phys()