12b4ffbf6SChris Packham /* SPDX-License-Identifier: GPL-2.0 */ 22b4ffbf6SChris Packham /* 32b4ffbf6SChris Packham * Copyright (C) Marvell International Ltd. and its affiliates 42b4ffbf6SChris Packham */ 52b4ffbf6SChris Packham 62b4ffbf6SChris Packham #ifndef _MV_DDR_REGS_H 72b4ffbf6SChris Packham #define _MV_DDR_REGS_H 82b4ffbf6SChris Packham 92b4ffbf6SChris Packham #define GLOB_CTRL_STATUS_REG 0x1030 102b4ffbf6SChris Packham #define TRAINING_TRIGGER_OFFS 0 112b4ffbf6SChris Packham #define TRAINING_TRIGGER_MASK 0x1 122b4ffbf6SChris Packham #define TRAINING_TRIGGER_ENA 1 132b4ffbf6SChris Packham #define TRAINING_DONE_OFFS 1 142b4ffbf6SChris Packham #define TRAINING_DONE_MASK 0x1 152b4ffbf6SChris Packham #define TRAINING_DONE_DONE 1 162b4ffbf6SChris Packham #define TRAINING_DONE_NOT_DONE 0 172b4ffbf6SChris Packham #define TRAINING_RESULT_OFFS 2 182b4ffbf6SChris Packham #define TRAINING_RESULT_MASK 0x1 192b4ffbf6SChris Packham #define TRAINING_RESULT_PASS 0 202b4ffbf6SChris Packham #define TRAINING_RESULT_FAIL 1 212b4ffbf6SChris Packham 222b4ffbf6SChris Packham #define GENERAL_TRAINING_OPCODE_REG 0x1034 232b4ffbf6SChris Packham 242b4ffbf6SChris Packham #define OPCODE_REG0_BASE 0x1038 252b4ffbf6SChris Packham #define OPCODE_REG0_REG(obj) (OPCODE_REG0_BASE + (obj) * 0x4) 262b4ffbf6SChris Packham 272b4ffbf6SChris Packham #define OPCODE_REG1_BASE 0x10b0 282b4ffbf6SChris Packham #define OPCODE_REG1_REG(obj) (OPCODE_REG1_BASE + (obj) * 0x4) 292b4ffbf6SChris Packham 302b4ffbf6SChris Packham #define CAL_PHY_BASE 0x10c0 312b4ffbf6SChris Packham #define CAL_PHY_REG(obj) (CAL_PHY_BASE + (obj) * 0x4) 322b4ffbf6SChris Packham 332b4ffbf6SChris Packham #define WL_DONE_CNTR_REF_REG 0x10f8 342b4ffbf6SChris Packham #define ODPG_WR_RD_MODE_ENA_REG 0x10fc 352b4ffbf6SChris Packham 362b4ffbf6SChris Packham #define SDRAM_CFG_REG 0x1400 372b4ffbf6SChris Packham #define REFRESH_OFFS 0 382b4ffbf6SChris Packham #define REFRESH_MASK 0x3fff 392b4ffbf6SChris Packham #define DRAM_TYPE_OFFS 14 402b4ffbf6SChris Packham #define DRAM_TYPE_MASK 0x1 412b4ffbf6SChris Packham #define BUS_IN_USE_OFFS 15 422b4ffbf6SChris Packham #define BUS_IN_USE_MASK 0x1 432b4ffbf6SChris Packham #define CPU_2DRAM_WR_BUFF_CUT_TH_OFFS 16 442b4ffbf6SChris Packham #define CPU_2DRAM_WR_BUFF_CUT_TH_MASK 0x1 452b4ffbf6SChris Packham #define REG_DIMM_OFFS 17 462b4ffbf6SChris Packham #define REG_DIMM_MASK 0x1 472b4ffbf6SChris Packham #define ECC_OFFS 18 482b4ffbf6SChris Packham #define ECC_MASK 0x1 492b4ffbf6SChris Packham #define IGNORE_ERRORS_OFFS 19 502b4ffbf6SChris Packham #define IGNORE_ERRORS_MASK 0x1 512b4ffbf6SChris Packham #define DRAM_TYPE_HIGH_OFFS 20 522b4ffbf6SChris Packham #define DRAM_TYPE_HIGH_MASK 0x1 532b4ffbf6SChris Packham #define SELF_REFRESH_MODE_OFFS 24 542b4ffbf6SChris Packham #define SELF_REFRESH_MODE_MASK 0x1 552b4ffbf6SChris Packham #define CPU_RD_PER_PROP_OFFS 25 562b4ffbf6SChris Packham #define CPU_RD_PER_PROP_MASK 0x1 572b4ffbf6SChris Packham #define DDR4_EMULATION_OFFS 26 582b4ffbf6SChris Packham #define DDR4_EMULATION_MASK 0x1 592b4ffbf6SChris Packham #define PHY_RF_RST_OFFS 27 602b4ffbf6SChris Packham #define PHY_RF_RST_MASK 0x1 612b4ffbf6SChris Packham #define PUP_RST_DIVIDER_OFFS 28 622b4ffbf6SChris Packham #define PUP_RST_DIVIDER_MASK 0x1 632b4ffbf6SChris Packham #define DATA_PUP_WR_RESET_OFFS 29 642b4ffbf6SChris Packham #define DATA_PUP_WR_RESET_MASK 0x1 652b4ffbf6SChris Packham #define DATA_PUP_RD_RESET_OFFS 30 662b4ffbf6SChris Packham #define DATA_PUP_RD_RESET_MASK 0x1 672b4ffbf6SChris Packham #define DATA_PUP_RD_RESET_ENA 0x0 682b4ffbf6SChris Packham #define DATA_PUP_RD_RESET_DIS 0x1 692b4ffbf6SChris Packham #define IO_BIST_OFFS 31 702b4ffbf6SChris Packham #define DATA_PUP_RD_RESET_MASK 0x1 712b4ffbf6SChris Packham 722b4ffbf6SChris Packham #define DUNIT_CTRL_LOW_REG 0x1404 732b4ffbf6SChris Packham 742b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_REG 0x1408 752b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TRAS_OFFS 0 762b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TRAS_MASK 0xf 772b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TRCD_OFFS 4 782b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TRCD_MASK 0xf 792b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TRCD_OFFS 22 802b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TRCD_MASK 0x1 812b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TRP_OFFS 8 822b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TRP_MASK 0xf 832b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TRP_OFFS 23 842b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TRP_MASK 0x1 852b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TWR_OFFS 12 862b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TWR_MASK 0xf 872b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TWTR_OFFS 16 882b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TWTR_MASK 0xf 892b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TRAS_HIGH_OFFS 20 902b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TRAS_HIGH_MASK 0x3 912b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TRRD_OFFS 24 922b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TRRD_MASK 0xf 932b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TRTP_OFFS 28 942b4ffbf6SChris Packham #define SDRAM_TIMING_LOW_TRTP_MASK 0xf 952b4ffbf6SChris Packham 962b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_REG 0x140c 972b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TRFC_OFFS 0 982b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TRFC_MASK 0x7f 992b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TR2R_OFFS 7 1002b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TR2R_MASK 0x3 1012b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TR2W_W2R_OFFS 9 1022b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TR2W_W2R_MASK 0x3 1032b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TW2W_OFFS 11 1042b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TW2W_MASK 0x1f 1052b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TRFC_HIGH_OFFS 16 1062b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TRFC_HIGH_MASK 0x7 1072b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TR2R_HIGH_OFFS 19 1082b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TR2R_HIGH_MASK 0x7 1092b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TR2W_W2R_HIGH_OFFS 22 1102b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TR2W_W2R_HIGH_MASK 0x7 1112b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TMOD_OFFS 25 1122b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TMOD_MASK 0xf 1132b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TMOD_HIGH_OFFS 30 1142b4ffbf6SChris Packham #define SDRAM_TIMING_HIGH_TMOD_HIGH_MASK 0x3 1152b4ffbf6SChris Packham 1162b4ffbf6SChris Packham #define SDRAM_ADDR_CTRL_REG 0x1410 1172b4ffbf6SChris Packham #define CS_STRUCT_BASE 0 1182b4ffbf6SChris Packham #define CS_STRUCT_OFFS(cs) (CS_STRUCT_BASE + (cs) * 4) 1192b4ffbf6SChris Packham #define CS_STRUCT_MASK 0x3 1202b4ffbf6SChris Packham #define CS_SIZE_BASE 2 1212b4ffbf6SChris Packham #define CS_SIZE_OFFS(cs) (CS_SIZE_BASE + (cs) * 4) 1222b4ffbf6SChris Packham #define CS_SIZE_MASK 0x3 1232b4ffbf6SChris Packham #define CS_SIZE_HIGH_BASE 20 1242b4ffbf6SChris Packham #define CS_SIZE_HIGH_OFFS(cs) (CS_SIZE_HIGH_BASE + (cs)) 1252b4ffbf6SChris Packham #define CS_SIZE_HIGH_MASK 0x1 1262b4ffbf6SChris Packham #define T_FAW_OFFS 24 1272b4ffbf6SChris Packham #define T_FAW_MASK 0x7f 1282b4ffbf6SChris Packham 1292b4ffbf6SChris Packham #define SDRAM_OPEN_PAGES_CTRL_REG 0x1414 1302b4ffbf6SChris Packham 1312b4ffbf6SChris Packham #define SDRAM_OP_REG 0x1418 1322b4ffbf6SChris Packham #define SDRAM_OP_CMD_OFFS 0 1332b4ffbf6SChris Packham #define SDRAM_OP_CMD_MASK 0x1f 1342b4ffbf6SChris Packham #define SDRAM_OP_CMD_CS_BASE 8 1352b4ffbf6SChris Packham #define SDRAM_OP_CMD_CS_OFFS(cs) (SDRAM_OP_CMD_CS_BASE + (cs)) 1362b4ffbf6SChris Packham #define SDRAM_OP_CMD_CS_MASK 0x1 137*ebb1a593SChris Packham #define SDRAM_OP_CMD_ALL_CS_MASK 0xf 1382b4ffbf6SChris Packham enum { 1392b4ffbf6SChris Packham CMD_NORMAL, 1402b4ffbf6SChris Packham CMD_PRECHARGE, 1412b4ffbf6SChris Packham CMD_REFRESH, 1422b4ffbf6SChris Packham CMD_DDR3_DDR4_MR0, 1432b4ffbf6SChris Packham CMD_DDR3_DDR4_MR1, 1442b4ffbf6SChris Packham CMD_NOP, 1452b4ffbf6SChris Packham CMD_RES_0X6, 1462b4ffbf6SChris Packham CMD_SELFREFRESH, 1472b4ffbf6SChris Packham CMD_DDR3_DDR4_MR2, 1482b4ffbf6SChris Packham CMD_DDR3_DDR4_MR3, 1492b4ffbf6SChris Packham CMD_ACT_PDE, 1502b4ffbf6SChris Packham CMD_PRE_PDE, 1512b4ffbf6SChris Packham CMD_ZQCL, 1522b4ffbf6SChris Packham CMD_ZQCS, 1532b4ffbf6SChris Packham CMD_CWA, 1542b4ffbf6SChris Packham CMD_RES_0XF, 1552b4ffbf6SChris Packham CMD_DDR4_MR4, 1562b4ffbf6SChris Packham CMD_DDR4_MR5, 1572b4ffbf6SChris Packham CMD_DDR4_MR6, 1582b4ffbf6SChris Packham DDR4_MPR_WR 1592b4ffbf6SChris Packham }; 1602b4ffbf6SChris Packham 1612b4ffbf6SChris Packham #define DUNIT_CTRL_HIGH_REG 0x1424 1622b4ffbf6SChris Packham #define CPU_INTERJECTION_ENA_OFFS 3 1632b4ffbf6SChris Packham #define CPU_INTERJECTION_ENA_MASK 0x1 1642b4ffbf6SChris Packham #define CPU_INTERJECTION_ENA_SPLIT_ENA 0 1652b4ffbf6SChris Packham #define CPU_INTERJECTION_ENA_SPLIT_DIS 1 1662b4ffbf6SChris Packham 1672b4ffbf6SChris Packham #define DDR_ODT_TIMING_LOW_REG 0x1428 1682b4ffbf6SChris Packham 1692b4ffbf6SChris Packham #define DDR_TIMING_REG 0x142c 1702b4ffbf6SChris Packham #define DDR_TIMING_TCCD_OFFS 18 1712b4ffbf6SChris Packham #define DDR_TIMING_TCCD_MASK 0x7 1722b4ffbf6SChris Packham #define DDR_TIMING_TPD_OFFS 0 1732b4ffbf6SChris Packham #define DDR_TIMING_TPD_MASK 0xf 1742b4ffbf6SChris Packham #define DDR_TIMING_TXPDLL_OFFS 4 1752b4ffbf6SChris Packham #define DDR_TIMING_TXPDLL_MASK 0x1f 1762b4ffbf6SChris Packham 1772b4ffbf6SChris Packham #define DDR_ODT_TIMING_HIGH_REG 0x147c 1782b4ffbf6SChris Packham 1792b4ffbf6SChris Packham #define SDRAM_INIT_CTRL_REG 0x1480 1802b4ffbf6SChris Packham #define DRAM_RESET_MASK_OFFS 1 1812b4ffbf6SChris Packham #define DRAM_RESET_MASK_MASK 0x1 1822b4ffbf6SChris Packham #define DRAM_RESET_MASK_NORMAL 0 1832b4ffbf6SChris Packham #define DRAM_RESET_MASK_MASKED 1 1842b4ffbf6SChris Packham 1852b4ffbf6SChris Packham #define SDRAM_ODT_CTRL_HIGH_REG 0x1498 1862b4ffbf6SChris Packham #define DUNIT_ODT_CTRL_REG 0x149c 1872b4ffbf6SChris Packham #define RD_BUFFER_SEL_REG 0x14a4 1882b4ffbf6SChris Packham #define AXI_CTRL_REG 0x14a8 1892b4ffbf6SChris Packham #define DUNIT_MMASK_REG 0x14b0 1902b4ffbf6SChris Packham 1912b4ffbf6SChris Packham #define HORZ_SSTL_CAL_MACH_CTRL_REG 0x14c8 1922b4ffbf6SChris Packham #define HORZ_POD_CAL_MACH_CTRL_REG 0x17c8 1932b4ffbf6SChris Packham #define VERT_SSTL_CAL_MACH_CTRL_REG 0x1dc8 1942b4ffbf6SChris Packham #define VERT_POD_CAL_MACH_CTRL_REG 0x1ec8 1952b4ffbf6SChris Packham 1962b4ffbf6SChris Packham #define MAIN_PADS_CAL_MACH_CTRL_REG 0x14cc 1972b4ffbf6SChris Packham #define DYN_PADS_CAL_ENABLE_OFFS 0 1982b4ffbf6SChris Packham #define DYN_PADS_CAL_ENABLE_MASK 0x1 1992b4ffbf6SChris Packham #define DYN_PADS_CAL_ENABLE_DIS 0 2002b4ffbf6SChris Packham #define DYN_PADS_CAL_ENABLE_ENA 1 2012b4ffbf6SChris Packham #define PADS_RECAL_OFFS 1 2022b4ffbf6SChris Packham #define PADS_RECAL_MASK 0x1 2032b4ffbf6SChris Packham #define DYN_PADS_CAL_BLOCK_OFFS 2 2042b4ffbf6SChris Packham #define DYN_PADS_CAL_BLOCK_MASK 0x1 2052b4ffbf6SChris Packham #define CAL_UPDATE_CTRL_OFFS 3 2062b4ffbf6SChris Packham #define CAL_UPDATE_CTRL_MASK 0x3 2072b4ffbf6SChris Packham #define CAL_UPDATE_CTRL_INT 1 2082b4ffbf6SChris Packham #define CAL_UPDATE_CTRL_EXT 2 2092b4ffbf6SChris Packham #define DYN_PADS_CAL_CNTR_OFFS 13 2102b4ffbf6SChris Packham #define DYN_PADS_CAL_CNTR_MASK 0x3ffff 2112b4ffbf6SChris Packham #define CAL_MACH_STATUS_OFFS 31 2122b4ffbf6SChris Packham #define CAL_MACH_STATUS_MASK 0x1 2132b4ffbf6SChris Packham #define CAL_MACH_BUSY 0 2142b4ffbf6SChris Packham #define CAL_MACH_RDY 1 2152b4ffbf6SChris Packham 2162b4ffbf6SChris Packham #define DRAM_DLL_TIMING_REG 0x14e0 2172b4ffbf6SChris Packham #define DRAM_ZQ_INIT_TIMIMG_REG 0x14e4 2182b4ffbf6SChris Packham #define DRAM_ZQ_TIMING_REG 0x14e8 2192b4ffbf6SChris Packham 2202b4ffbf6SChris Packham #define DRAM_LONG_TIMING_REG 0x14ec 2212b4ffbf6SChris Packham #define DDR4_TRRD_L_OFFS 0 2222b4ffbf6SChris Packham #define DDR4_TRRD_L_MASK 0xf 2232b4ffbf6SChris Packham #define DDR4_TWTR_L_OFFS 4 2242b4ffbf6SChris Packham #define DDR4_TWTR_L_MASK 0xf 2252b4ffbf6SChris Packham 2262b4ffbf6SChris Packham #define DDR_IO_REG 0x1524 2272b4ffbf6SChris Packham #define DFS_REG 0x1528 2282b4ffbf6SChris Packham 2292b4ffbf6SChris Packham #define RD_DATA_SMPL_DLYS_REG 0x1538 2302b4ffbf6SChris Packham #define RD_SMPL_DLY_CS_BASE 0 2312b4ffbf6SChris Packham #define RD_SMPL_DLY_CS_OFFS(cs) (RD_SMPL_DLY_CS_BASE + (cs) * 8) 2322b4ffbf6SChris Packham #define RD_SMPL_DLY_CS_MASK 0x1f 2332b4ffbf6SChris Packham 2342b4ffbf6SChris Packham #define RD_DATA_RDY_DLYS_REG 0x153c 2352b4ffbf6SChris Packham #define RD_RDY_DLY_CS_BASE 0 2362b4ffbf6SChris Packham #define RD_RDY_DLY_CS_OFFS(cs) (RD_RDY_DLY_CS_BASE + (cs) * 8) 2372b4ffbf6SChris Packham #define RD_RDY_DLY_CS_MASK 0x1f 2382b4ffbf6SChris Packham 2392b4ffbf6SChris Packham #define TRAINING_REG 0x15b0 2402b4ffbf6SChris Packham #define TRN_START_OFFS 31 2412b4ffbf6SChris Packham #define TRN_START_MASK 0x1 2422b4ffbf6SChris Packham #define TRN_START_ENA 1 2432b4ffbf6SChris Packham #define TRN_START_DIS 0 2442b4ffbf6SChris Packham 2452b4ffbf6SChris Packham #define TRAINING_SW_1_REG 0x15b4 2462b4ffbf6SChris Packham 2472b4ffbf6SChris Packham #define TRAINING_SW_2_REG 0x15b8 2482b4ffbf6SChris Packham #define TRAINING_ECC_MUX_OFFS 1 2492b4ffbf6SChris Packham #define TRAINING_ECC_MUX_MASK 0x1 2502b4ffbf6SChris Packham #define TRAINING_ECC_MUX_DIS 0 2512b4ffbf6SChris Packham #define TRAINING_ECC_MUX_ENA 1 2522b4ffbf6SChris Packham #define TRAINING_SW_OVRD_OFFS 0 2532b4ffbf6SChris Packham #define TRAINING_SW_OVRD_MASK 0x1 2542b4ffbf6SChris Packham #define TRAINING_SW_OVRD_DIS 0 2552b4ffbf6SChris Packham #define TRAINING_SW_OVRD_ENA 1 2562b4ffbf6SChris Packham 2572b4ffbf6SChris Packham #define TRAINING_PATTERN_BASE_ADDR_REG 0x15bc 2582b4ffbf6SChris Packham #define TRAINING_DBG_1_REG 0x15c0 2592b4ffbf6SChris Packham #define TRAINING_DBG_2_REG 0x15c4 2602b4ffbf6SChris Packham 2612b4ffbf6SChris Packham #define TRAINING_DBG_3_REG 0x15c8 2622b4ffbf6SChris Packham #define TRN_DBG_RDY_INC_PH_2TO1_BASE 0 2632b4ffbf6SChris Packham #define TRN_DBG_RDY_INC_PH_2TO1_OFFS(phase) (TRN_DBG_RDY_INC_PH_2TO1_BASE + (phase) * 3) 2642b4ffbf6SChris Packham #define TRN_DBG_RDY_INC_PH_2TO1_MASK 0x7 2652b4ffbf6SChris Packham 2662b4ffbf6SChris Packham #define DDR3_RANK_CTRL_REG 0x15e0 2672b4ffbf6SChris Packham #define CS_EXIST_BASE 0 2682b4ffbf6SChris Packham #define CS_EXIST_OFFS(cs) (CS_EXIST_BASE + (cs)) 2692b4ffbf6SChris Packham #define CS_EXIST_MASK 0x1 2702b4ffbf6SChris Packham 2712b4ffbf6SChris Packham #define ZQC_CFG_REG 0x15e4 2722b4ffbf6SChris Packham #define DRAM_PHY_CFG_REG 0x15ec 2732b4ffbf6SChris Packham #define ODPG_CTRL_CTRL_REG 0x1600 274*ebb1a593SChris Packham #define ODPG_CTRL_AUTO_REFRESH_OFFS 21 275*ebb1a593SChris Packham #define ODPG_CTRL_AUTO_REFRESH_MASK 0x1 276*ebb1a593SChris Packham #define ODPG_CTRL_AUTO_REFRESH_DIS 1 277*ebb1a593SChris Packham #define ODPG_CTRL_AUTO_REFRESH_ENA 0 2782b4ffbf6SChris Packham 2792b4ffbf6SChris Packham #define ODPG_DATA_CTRL_REG 0x1630 2802b4ffbf6SChris Packham #define ODPG_WRBUF_WR_CTRL_OFFS 0 2812b4ffbf6SChris Packham #define ODPG_WRBUF_WR_CTRL_MASK 0x1 2822b4ffbf6SChris Packham #define ODPG_WRBUF_WR_CTRL_DIS 0 2832b4ffbf6SChris Packham #define ODPG_WRBUF_WR_CTRL_ENA 1 2842b4ffbf6SChris Packham #define ODPG_WRBUF_RD_CTRL_OFFS 1 2852b4ffbf6SChris Packham #define ODPG_WRBUF_RD_CTRL_MASK 0x1 2862b4ffbf6SChris Packham #define ODPG_WRBUF_RD_CTRL_DIS 0 2872b4ffbf6SChris Packham #define ODPG_WRBUF_RD_CTRL_ENA 1 2882b4ffbf6SChris Packham #define ODPG_DATA_CBDEL_OFFS 15 2892b4ffbf6SChris Packham #define ODPG_DATA_CBDEL_MASK 0x3f 2902b4ffbf6SChris Packham #define ODPG_MODE_OFFS 25 2912b4ffbf6SChris Packham #define ODPG_MODE_MASK 0x1 2922b4ffbf6SChris Packham #define ODPG_MODE_RX 0 2932b4ffbf6SChris Packham #define ODPG_MODE_TX 1 2942b4ffbf6SChris Packham #define ODPG_DATA_CS_OFFS 26 2952b4ffbf6SChris Packham #define ODPG_DATA_CS_MASK 0x3 2962b4ffbf6SChris Packham #define ODPG_DISABLE_OFFS 30 2972b4ffbf6SChris Packham #define ODPG_DISABLE_MASK 0x1 2982b4ffbf6SChris Packham #define ODPG_DISABLE_DIS 1 2992b4ffbf6SChris Packham #define ODPG_ENABLE_OFFS 31 3002b4ffbf6SChris Packham #define ODPG_ENABLE_MASK 0x1 3012b4ffbf6SChris Packham #define ODPG_ENABLE_ENA 1 3022b4ffbf6SChris Packham 3032b4ffbf6SChris Packham #define ODPG_DATA_BUFFER_OFFS_REG 0x1638 3042b4ffbf6SChris Packham #define ODPG_DATA_BUFFER_SIZE_REG 0x163c 3052b4ffbf6SChris Packham #define PHY_LOCK_STATUS_REG 0x1674 3062b4ffbf6SChris Packham 3072b4ffbf6SChris Packham #define PHY_REG_FILE_ACCESS_REG 0x16a0 3082b4ffbf6SChris Packham #define PRFA_DATA_OFFS 0 3092b4ffbf6SChris Packham #define PRFA_DATA_MASK 0xffff 3102b4ffbf6SChris Packham #define PRFA_REG_NUM_OFFS 16 3112b4ffbf6SChris Packham #define PRFA_REG_NUM_MASK 0x3f 3122b4ffbf6SChris Packham #define PRFA_PUP_NUM_OFFS 22 3132b4ffbf6SChris Packham #define PRFA_PUP_NUM_MASK 0xf 3142b4ffbf6SChris Packham #define PRFA_PUP_CTRL_DATA_OFFS 26 3152b4ffbf6SChris Packham #define PRFA_PUP_CTRL_DATA_MASK 0x1 3162b4ffbf6SChris Packham #define PRFA_PUP_BCAST_WR_ENA_OFFS 27 3172b4ffbf6SChris Packham #define PRFA_PUP_BCAST_WR_ENA_MASK 0x1 3182b4ffbf6SChris Packham #define PRFA_REG_NUM_HI_OFFS 28 3192b4ffbf6SChris Packham #define PRFA_REG_NUM_HI_MASK 0x3 3202b4ffbf6SChris Packham #define PRFA_TYPE_OFFS 30 3212b4ffbf6SChris Packham #define PRFA_TYPE_MASK 0x1 3222b4ffbf6SChris Packham #define PRFA_REQ_OFFS 31 3232b4ffbf6SChris Packham #define PRFA_REQ_MASK 0x1 3242b4ffbf6SChris Packham #define PRFA_REQ_DIS 0x0 3252b4ffbf6SChris Packham #define PRFA_REQ_ENA 0x1 3262b4ffbf6SChris Packham 3272b4ffbf6SChris Packham #define TRAINING_WL_REG 0x16ac 3282b4ffbf6SChris Packham 3292b4ffbf6SChris Packham #define ODPG_DATA_WR_ADDR_REG 0x16b0 3302b4ffbf6SChris Packham #define ODPG_DATA_WR_ACK_OFFS 0 3312b4ffbf6SChris Packham #define ODPG_DATA_WR_ACK_MASK 0x7f 3322b4ffbf6SChris Packham #define ODPG_DATA_WR_DATA_OFFS 8 3332b4ffbf6SChris Packham #define ODPG_DATA_WR_DATA_MASK 0xff 3342b4ffbf6SChris Packham 3352b4ffbf6SChris Packham #define ODPG_DATA_WR_DATA_HIGH_REG 0x16b4 3362b4ffbf6SChris Packham #define ODPG_DATA_WR_DATA_LOW_REG 0x16b8 3372b4ffbf6SChris Packham #define ODPG_DATA_RX_WORD_ERR_ADDR_REG 0x16bc 3382b4ffbf6SChris Packham #define ODPG_DATA_RX_WORD_ERR_CNTR_REG 0x16c0 3392b4ffbf6SChris Packham #define ODPG_DATA_RX_WORD_ERR_DATA_HIGH_REG 0x16c4 3402b4ffbf6SChris Packham #define ODPG_DATA_RX_WORD_ERR_DATA_LOW_REG 0x16c8 3412b4ffbf6SChris Packham #define ODPG_DATA_WR_DATA_ERR_REG 0x16cc 3422b4ffbf6SChris Packham 3432b4ffbf6SChris Packham #define DUAL_DUNIT_CFG_REG 0x16d8 3442b4ffbf6SChris Packham #define FC_SAMPLE_STAGES_OFFS 0 3452b4ffbf6SChris Packham #define FC_SAMPLE_STAGES_MASK 0x7 3462b4ffbf6SChris Packham #define SINGLE_CS_PIN_OFFS 3 3472b4ffbf6SChris Packham #define SINGLE_CS_PIN_MASK 0x1 3482b4ffbf6SChris Packham #define SINGLE_CS_ENA 1 3492b4ffbf6SChris Packham #define TUNING_ACTIVE_SEL_OFFS 6 3502b4ffbf6SChris Packham #define TUNING_ACTIVE_SEL_MASK 0x1 3512b4ffbf6SChris Packham #define TUNING_ACTIVE_SEL_MC 0 3522b4ffbf6SChris Packham #define TUNING_ACTIVE_SEL_TIP 1 3532b4ffbf6SChris Packham 3542b4ffbf6SChris Packham #define WL_DQS_PATTERN_REG 0x16dc 3552b4ffbf6SChris Packham #define ODPG_DONE_STATUS_REG 0x16fc 3562b4ffbf6SChris Packham #define ODPG_DONE_STATUS_BIT_OFFS 0 3572b4ffbf6SChris Packham #define ODPG_DONE_STATUS_BIT_MASK 0x1 3582b4ffbf6SChris Packham #define ODPG_DONE_STATUS_BIT_CLR 0 3592b4ffbf6SChris Packham #define ODPG_DONE_STATUS_BIT_SET 1 3602b4ffbf6SChris Packham 3612b4ffbf6SChris Packham #define RESULT_CTRL_BASE 0x1830 3622b4ffbf6SChris Packham #define BLOCK_STATUS_OFFS 25 3632b4ffbf6SChris Packham #define BLOCK_STATUS_MASK 0x1 3642b4ffbf6SChris Packham #define BLOCK_STATUS_LOCK 1 3652b4ffbf6SChris Packham #define BLOCK_STATUS_NOT_LOCKED 0 3662b4ffbf6SChris Packham 3672b4ffbf6SChris Packham #define MR0_REG 0x15d0 3682b4ffbf6SChris Packham #define MR1_REG 0x15d4 3692b4ffbf6SChris Packham #define MR2_REG 0x15d8 3702b4ffbf6SChris Packham #define MR3_REG 0x15dc 3712b4ffbf6SChris Packham #define MRS0_CMD 0x3 3722b4ffbf6SChris Packham #define MRS1_CMD 0x4 3732b4ffbf6SChris Packham #define MRS2_CMD 0x8 3742b4ffbf6SChris Packham #define MRS3_CMD 0x9 3752b4ffbf6SChris Packham 3762b4ffbf6SChris Packham 3772b4ffbf6SChris Packham #define DRAM_PINS_MUX_REG 0x19d4 3782b4ffbf6SChris Packham #define CTRL_PINS_MUX_OFFS 0 3792b4ffbf6SChris Packham #define CTRL_PINS_MUX_MASK 0x3 3802b4ffbf6SChris Packham enum { 3812b4ffbf6SChris Packham DUNIT_DDR3_ON_BOARD, 3822b4ffbf6SChris Packham DUNIT_DDR3_DIMM, 3832b4ffbf6SChris Packham DUNIT_DDR4_ON_BOARD, 3842b4ffbf6SChris Packham DUNIT_DDR4_DIMM 3852b4ffbf6SChris Packham }; 3862b4ffbf6SChris Packham 3872b4ffbf6SChris Packham /* ddr phy registers */ 3882b4ffbf6SChris Packham #define WL_PHY_BASE 0x0 3892b4ffbf6SChris Packham #define WL_PHY_REG(cs) (WL_PHY_BASE + (cs) * 0x4) 3902b4ffbf6SChris Packham #define WR_LVL_PH_SEL_OFFS 6 3912b4ffbf6SChris Packham #define WR_LVL_PH_SEL_MASK 0x7 3922b4ffbf6SChris Packham #define WR_LVL_PH_SEL_PHASE1 1 3932b4ffbf6SChris Packham #define WR_LVL_REF_DLY_OFFS 0 3942b4ffbf6SChris Packham #define WR_LVL_REF_DLY_MASK 0x1f 3952b4ffbf6SChris Packham #define CTRL_CENTER_DLY_OFFS 10 3962b4ffbf6SChris Packham #define CTRL_CENTER_DLY_MASK 0x1f 3972b4ffbf6SChris Packham #define CTRL_CENTER_DLY_INV_OFFS 15 3982b4ffbf6SChris Packham #define CTRL_CENTER_DLY_INV_MASK 0x1 3992b4ffbf6SChris Packham 4002b4ffbf6SChris Packham #define CTX_PHY_BASE 0x1 4012b4ffbf6SChris Packham #define CTX_PHY_REG(cs) (CTX_PHY_BASE + (cs) * 0x4) 4022b4ffbf6SChris Packham 4032b4ffbf6SChris Packham #define RL_PHY_BASE 0x2 4042b4ffbf6SChris Packham #define RL_PHY_REG(cs) (RL_PHY_BASE + (cs) * 0x4) 4052b4ffbf6SChris Packham #define RL_REF_DLY_OFFS 0 4062b4ffbf6SChris Packham #define RL_REF_DLY_MASK 0x1f 4072b4ffbf6SChris Packham #define RL_PH_SEL_OFFS 6 4082b4ffbf6SChris Packham #define RL_PH_SEL_MASK 0x7 4092b4ffbf6SChris Packham 4102b4ffbf6SChris Packham #define CRX_PHY_BASE 0x3 4112b4ffbf6SChris Packham #define CRX_PHY_REG(cs) (CRX_PHY_BASE + (cs) * 0x4) 4122b4ffbf6SChris Packham 4132b4ffbf6SChris Packham #define PHY_CTRL_PHY_REG 0x90 414*ebb1a593SChris Packham #define INV_PAD0_OFFS 2 415*ebb1a593SChris Packham #define INV_PAD1_OFFS 3 416*ebb1a593SChris Packham #define INV_PAD2_OFFS 4 417*ebb1a593SChris Packham #define INV_PAD3_OFFS 5 418*ebb1a593SChris Packham #define INV_PAD4_OFFS 6 419*ebb1a593SChris Packham #define INV_PAD5_OFFS 7 420*ebb1a593SChris Packham #define INV_PAD6_OFFS 8 421*ebb1a593SChris Packham #define INV_PAD7_OFFS 9 422*ebb1a593SChris Packham #define INV_PAD8_OFFS 10 423*ebb1a593SChris Packham #define INV_PAD9_OFFS 11 424*ebb1a593SChris Packham #define INV_PAD10_OFFS 12 425*ebb1a593SChris Packham #define INV_PAD_MASK 0x1 426*ebb1a593SChris Packham #define INVERT_PAD 1 427*ebb1a593SChris Packham 4282b4ffbf6SChris Packham #define ADLL_CFG0_PHY_REG 0x92 4292b4ffbf6SChris Packham #define ADLL_CFG1_PHY_REG 0x93 4302b4ffbf6SChris Packham #define ADLL_CFG2_PHY_REG 0x94 4312b4ffbf6SChris Packham #define CMOS_CONFIG_PHY_REG 0xa2 4322b4ffbf6SChris Packham #define PAD_ZRI_CAL_PHY_REG 0xa4 4332b4ffbf6SChris Packham #define PAD_ODT_CAL_PHY_REG 0xa6 4342b4ffbf6SChris Packham #define PAD_CFG_PHY_REG 0xa8 4352b4ffbf6SChris Packham #define PAD_PRE_DISABLE_PHY_REG 0xa9 4362b4ffbf6SChris Packham #define TEST_ADLL_PHY_REG 0xbf 4372b4ffbf6SChris Packham 4382b4ffbf6SChris Packham #define VREF_PHY_BASE 0xd0 4392b4ffbf6SChris Packham #define VREF_PHY_REG(cs, bit) (VREF_PHY_BASE + (cs) * 12 + bit) 4402b4ffbf6SChris Packham enum { 4412b4ffbf6SChris Packham DQSP_PAD = 4, 4422b4ffbf6SChris Packham DQSN_PAD 4432b4ffbf6SChris Packham }; 4442b4ffbf6SChris Packham 4452b4ffbf6SChris Packham #define VREF_BCAST_PHY_BASE 0xdb 4462b4ffbf6SChris Packham #define VREF_BCAST_PHY_REG(cs) (VREF_BCAST_PHY_BASE + (cs) * 12) 4472b4ffbf6SChris Packham 4482b4ffbf6SChris Packham #define PBS_TX_PHY_BASE 0x10 4492b4ffbf6SChris Packham #define PBS_TX_PHY_REG(cs, bit) (PBS_TX_PHY_BASE + (cs) * 0x10 + (bit)) 4502b4ffbf6SChris Packham 4512b4ffbf6SChris Packham #define PBS_TX_BCAST_PHY_BASE 0x1f 4522b4ffbf6SChris Packham #define PBS_TX_BCAST_PHY_REG(cs) (PBS_TX_BCAST_PHY_BASE + (cs) * 0x10) 4532b4ffbf6SChris Packham 4542b4ffbf6SChris Packham #define PBS_RX_PHY_BASE 0x50 4552b4ffbf6SChris Packham #define PBS_RX_PHY_REG(cs, bit) (PBS_RX_PHY_BASE + (cs) * 0x10 + (bit)) 4562b4ffbf6SChris Packham 4572b4ffbf6SChris Packham #define PBS_RX_BCAST_PHY_BASE 0x5f 4582b4ffbf6SChris Packham #define PBS_RX_BCAST_PHY_REG(cs) (PBS_RX_BCAST_PHY_BASE + (cs) * 0x10) 4592b4ffbf6SChris Packham 4602b4ffbf6SChris Packham #define RESULT_PHY_REG 0xc0 4612b4ffbf6SChris Packham #define RESULT_PHY_RX_OFFS 5 4622b4ffbf6SChris Packham #define RESULT_PHY_TX_OFFS 0 4632b4ffbf6SChris Packham 4642b4ffbf6SChris Packham 4652b4ffbf6SChris Packham #endif /* _MV_DDR_REGS_H */ 466