1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define TRAINING_TRIGGER_ENA			1
13 #define TRAINING_DONE_OFFS			1
15 #define TRAINING_DONE_DONE			1
20 #define TRAINING_RESULT_FAIL			1
118 #define CS_STRUCT_OFFS(cs)			(CS_STRUCT_BASE + (cs) * 4)  argument
121 #define CS_SIZE_OFFS(cs)			(CS_SIZE_BASE + (cs) * 4)  argument
124 #define CS_SIZE_HIGH_OFFS(cs)			(CS_SIZE_HIGH_BASE + (cs))  argument
135 #define SDRAM_OP_CMD_CS_OFFS(cs)		(SDRAM_OP_CMD_CS_BASE + (cs))  argument
165 #define CPU_INTERJECTION_ENA_SPLIT_DIS		1
180 #define DRAM_RESET_MASK_OFFS			1
183 #define DRAM_RESET_MASK_MASKED			1
200 #define DYN_PADS_CAL_ENABLE_ENA			1
201 #define PADS_RECAL_OFFS				1
207 #define CAL_UPDATE_CTRL_INT			1
214 #define CAL_MACH_RDY				1
231 #define RD_SMPL_DLY_CS_OFFS(cs)			(RD_SMPL_DLY_CS_BASE + (cs) * 8)  argument
236 #define RD_RDY_DLY_CS_OFFS(cs)			(RD_RDY_DLY_CS_BASE + (cs) * 8)  argument
242 #define TRN_START_ENA				1
248 #define TRAINING_ECC_MUX_OFFS			1
251 #define TRAINING_ECC_MUX_ENA			1
255 #define TRAINING_SW_OVRD_ENA			1
268 #define CS_EXIST_OFFS(cs)			(CS_EXIST_BASE + (cs))  argument
276 #define ODPG_CTRL_AUTO_REFRESH_DIS		1
283 #define ODPG_WRBUF_WR_CTRL_ENA			1
284 #define ODPG_WRBUF_RD_CTRL_OFFS			1
287 #define ODPG_WRBUF_RD_CTRL_ENA			1
293 #define ODPG_MODE_TX				1
298 #define ODPG_DISABLE_DIS			1
301 #define ODPG_ENABLE_ENA				1
348 #define SINGLE_CS_ENA				1
352 #define TUNING_ACTIVE_SEL_TIP			1
359 #define ODPG_DONE_STATUS_BIT_SET		1
364 #define BLOCK_STATUS_LOCK			1
389 #define WL_PHY_REG(cs)				(WL_PHY_BASE + (cs) * 0x4)  argument
392 #define WR_LVL_PH_SEL_PHASE1			1
401 #define CTX_PHY_REG(cs)				(CTX_PHY_BASE + (cs) * 0x4)  argument
404 #define RL_PHY_REG(cs)				(RL_PHY_BASE + (cs) * 0x4)  argument
411 #define CRX_PHY_REG(cs)				(CRX_PHY_BASE + (cs) * 0x4)  argument
426 #define INVERT_PAD				1
439 #define VREF_PHY_REG(cs, bit)			(VREF_PHY_BASE + (cs) * 12 + bit)  argument
446 #define VREF_BCAST_PHY_REG(cs)			(VREF_BCAST_PHY_BASE + (cs) * 12)  argument
449 #define PBS_TX_PHY_REG(cs, bit)			(PBS_TX_PHY_BASE + (cs) * 0x10 + (bit))  argument
452 #define PBS_TX_BCAST_PHY_REG(cs)		(PBS_TX_BCAST_PHY_BASE + (cs) * 0x10)  argument
455 #define PBS_RX_PHY_REG(cs, bit)			(PBS_RX_PHY_BASE + (cs) * 0x10 + (bit))  argument
458 #define PBS_RX_BCAST_PHY_REG(cs)		(PBS_RX_BCAST_PHY_BASE + (cs) * 0x10)  argument