| /openbmc/linux/Documentation/devicetree/bindings/pwm/ |
| H A D | mediatek,mt2712-pwm.yaml | 85 clocks = <&topckgen CLK_TOP_PWM_SEL>, <&pericfg CLK_PERI_PWM>,
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | mt7986-clk.h | 54 #define CLK_TOP_PWM_SEL 31 macro
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| H A D | mt7629-clk.h | 87 #define CLK_TOP_PWM_SEL 77 macro
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| H A D | mediatek,mt7981-clk.h | 94 #define CLK_TOP_PWM_SEL 81 macro
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| H A D | mt8516-clk.h | 188 #define CLK_TOP_PWM_SEL 156 macro
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| H A D | mt7622-clk.h | 72 #define CLK_TOP_PWM_SEL 60 macro
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| H A D | mediatek,mt6795-clk.h | 94 #define CLK_TOP_PWM_SEL 83 macro
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| H A D | mt8173-clk.h | 96 #define CLK_TOP_PWM_SEL 86 macro
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| H A D | mt6765-clk.h | 156 #define CLK_TOP_PWM_SEL 121 macro
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| H A D | mediatek,mt8365-clk.h | 99 #define CLK_TOP_PWM_SEL 89 macro
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| H A D | mt2712-clk.h | 133 #define CLK_TOP_PWM_SEL 102 macro
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| H A D | mt2701-clk.h | 94 #define CLK_TOP_PWM_SEL 83 macro
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| H A D | mt8192-clk.h | 66 #define CLK_TOP_PWM_SEL 54 macro
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| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 91 #define CLK_TOP_PWM_SEL 77 macro
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| H A D | mt7623-clk.h | 105 #define CLK_TOP_PWM_SEL 91 macro
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| /openbmc/linux/arch/arm/boot/dts/mediatek/ |
| H A D | mt7629.dtsi | 247 clocks = <&topckgen CLK_TOP_PWM_SEL>,
251 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt7986-topckgen.c | 186 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
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| H A D | clk-mt7981-topckgen.c | 303 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
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| H A D | clk-mt7622.c | 396 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
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| H A D | clk-mt6795-topckgen.c | 460 TOP_MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x50, 0, 2, 7, 0),
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| H A D | clk-mt8173-topckgen.c | 539 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
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| H A D | clk-mt8516.c | 421 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
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| H A D | clk-mt7629.c | 471 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
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| /openbmc/u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7629.c | 370 MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
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| /openbmc/linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt7986a.dtsi | 202 clocks = <&topckgen CLK_TOP_PWM_SEL>,
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