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/openbmc/linux/drivers/clk/qcom/
H A Dclk-spmi-pmic-div.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
24 struct clkdiv { struct
33 static inline struct clkdiv *to_clkdiv(struct clk_hw *hw) in to_clkdiv() argument
35 return container_of(hw, struct clkdiv, hw); in to_clkdiv()
43 return 1 << (div_factor - 1); in div_factor_to_div()
51 static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv) in is_spmi_pmic_clkdiv_enabled() argument
55 regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val); in is_spmi_pmic_clkdiv_enabled()
61 __spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable, in __spmi_pmic_clkdiv_set_enable_state() argument
65 unsigned int ns = clkdiv->cxo_period_ns; in __spmi_pmic_clkdiv_set_enable_state()
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-cavium.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 #define OCTEON_SPI_CFG(x) (x->regs.config)
27 #define OCTEON_SPI_STS(x) (x->regs.status)
28 #define OCTEON_SPI_TX(x) (x->regs.tx)
29 #define OCTEON_SPI_DAT0(x) (x->regs.data)
46 uint64_t clkdiv:13; member
78 uint64_t clkdiv:13;
85 uint64_t clkdiv:13; member
111 uint64_t clkdiv:13;
118 uint64_t clkdiv:13; member
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H A Dspi-cavium.c14 #include "spi-cavium.h"
24 mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS(p)); in octeon_spi_wait_ready()
33 struct spi_device *spi = msg->spi; in octeon_spi_do_transfer()
36 unsigned int clkdiv; in octeon_spi_do_transfer() local
44 mode = spi->mode; in octeon_spi_do_transfer()
48 clkdiv = p->sys_freq / (2 * xfer->speed_hz); in octeon_spi_do_transfer()
52 mpi_cfg.s.clkdiv = clkdiv; in octeon_spi_do_transfer()
61 p->cs_enax |= 1ull << (12 + spi_get_chipselect(spi, 0)); in octeon_spi_do_transfer()
62 mpi_cfg.u64 |= p->cs_enax; in octeon_spi_do_transfer()
64 if (mpi_cfg.u64 != p->last_cfg) { in octeon_spi_do_transfer()
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/openbmc/u-boot/drivers/mmc/
H A Dgen_atmel_mci.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de>
8 * Copyright (C) 2004-2006 Atmel Corporation
59 return readl(&mci->version) & 0x00000fff; in atmel_mci_get_version()
65 * - always when DEBUG is defined
66 * - on command errors
82 writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->blkr)), in mci_set_blklen()
83 &mci->blkr); in mci_set_blklen()
85 writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->mr)), &mci->mr); in mci_set_blklen()
94 struct mmc *mmc = &plat->mmc;
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H A Darm_pl180_mmci.c1 // SPDX-License-Identifier: GPL-2.0+
3 * ARM PrimeCell MultiMedia Card Interface - PL180
5 * Copyright (C) ST-Ericsson SA 2010
21 #include <asm-generic/gpio.h>
39 struct pl180_mmc_host *host = dev->priv; in wait_for_command_end()
42 if ((cmd->resp_type & MMC_RSP_PRESENT)) in wait_for_command_end()
48 hoststatus = readl(&host->base->status) & statusmask; in wait_for_command_end()
51 writel(statusmask, &host->base->status_clear); in wait_for_command_end()
53 debug("CMD%d time out\n", cmd->cmdidx); in wait_for_command_end()
54 return -ETIMEDOUT; in wait_for_command_end()
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,spmi-clkdiv.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,spmi-clkdiv.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Stephen Boyd <sboyd@kernel.org>
20 const: qcom,spmi-clkdiv
27 - description: Board XO source
29 clock-names:
31 - const: xo
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H A Drenesas,emev2-smu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
19 const: renesas,emev2-smu
24 '#address-cells':
27 '#size-cells':
31 - compatible
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H A Dbaikal,bt1-ccu-div.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
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/openbmc/linux/drivers/hwtracing/intel_th/
H A Dpti.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2016 Intel Corporation.
27 unsigned int clkdiv; member
46 return -EINVAL; in pti_width_mode()
54 return scnprintf(buf, PAGE_SIZE, "%d\n", pti_mode[pti->mode]); in mode_show()
72 pti->mode = ret; in mode_store()
85 return scnprintf(buf, PAGE_SIZE, "%d\n", pti->freeclk); in freerunning_clock_show()
100 pti->freeclk = !!val; in freerunning_clock_store()
113 return scnprintf(buf, PAGE_SIZE, "%d\n", 1u << pti->clkdiv); in clock_divider_show()
129 return -EINVAL; in clock_divider_store()
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/openbmc/u-boot/board/sbc8548/
H A Dsbc8548.c1 // SPDX-License-Identifier: GPL-2.0+
46 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ in checkboard()
47 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ in checkboard()
60 uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR; in local_bus_init() local
66 clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus; in local_bus_init()
68 debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz); in local_bus_init()
70 out_be32(&gur->lbiuiplldcr1, 0x00078080); in local_bus_init()
71 if (clkdiv == 16) { in local_bus_init()
72 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); in local_bus_init()
73 } else if (clkdiv == 8) { in local_bus_init()
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/openbmc/linux/arch/arm/boot/dts/renesas/
H A Demev2.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-a9";
35 clock-frequency = <533000000>;
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/openbmc/linux/sound/soc/intel/skylake/
H A Dskl-nhlt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * skl-nhlt.c - Intel SKL Platform NHLT parsing
12 #include <sound/intel-nhlt.h>
14 #include "skl-i2s.h"
33 struct nhlt_acpi_table *nhlt = (struct nhlt_acpi_table *)skl->nhlt; in skl_nhlt_update_topology_bin()
35 struct device *dev = bus->dev; in skl_nhlt_update_topology_bin()
38 nhlt->header.oem_id, nhlt->header.oem_table_id, in skl_nhlt_update_topology_bin()
39 nhlt->header.oem_revision); in skl_nhlt_update_topology_bin()
41 snprintf(skl->tplg_name, sizeof(skl->tplg_name), "%x-%.6s-%.8s-%d%s", in skl_nhlt_update_topology_bin()
42 skl->pci_id, nhlt->header.oem_id, nhlt->header.oem_table_id, in skl_nhlt_update_topology_bin()
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/openbmc/linux/drivers/w1/masters/
H A Dmxc_w1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
22 # define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
45 writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_reset_bus()
53 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_reset_bus()
55 /* PST bit is valid after the RPP bit is self-cleared */ in mxc_w1_ds2_reset_bus()
73 writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_touch_bit()
81 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); in mxc_w1_ds2_touch_bit()
83 /* RDST bit is valid after the WR1/RD bit is self-cleared */ in mxc_w1_ds2_touch_bit()
95 unsigned int clkdiv; in mxc_w1_probe() local
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/openbmc/linux/drivers/pwm/
H A Dpwm-tiehrpwm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
145 * set_prescale_div - Set up the prescaler divider function
153 unsigned int clkdiv, hspclkdiv; in set_prescale_div() local
155 for (clkdiv = 0; clkdiv <= CLKDIV_MAX; clkdiv++) { in set_prescale_div()
161 * CLKDIVIDER = (1), if clkdiv == 0 *OR* in set_prescale_div()
162 * (2 * clkdiv), if clkdiv != 0 in set_prescale_div()
168 *prescale_div = (1 << clkdiv) * in set_prescale_div()
171 *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) | in set_prescale_div()
196 if (pc->polarity[chan] == PWM_POLARITY_INVERSED) in configure_polarity()
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H A Dpwm-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
44 * struct pwm_mediatek_chip - struct representing PWM chip
82 ret = clk_prepare_enable(pc->clk_top); in pwm_mediatek_clk_enable()
86 ret = clk_prepare_enable(pc->clk_main); in pwm_mediatek_clk_enable()
90 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]); in pwm_mediatek_clk_enable()
97 clk_disable_unprepare(pc->clk_main); in pwm_mediatek_clk_enable()
99 clk_disable_unprepare(pc->clk_top); in pwm_mediatek_clk_enable()
109 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); in pwm_mediatek_clk_disable()
110 clk_disable_unprepare(pc->clk_main); in pwm_mediatek_clk_disable()
111 clk_disable_unprepare(pc->clk_top); in pwm_mediatek_clk_disable()
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/openbmc/linux/sound/soc/adi/
H A Daxi-spdif.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012-2013, Analog Devices Inc.
4 * Author: Lars-Peter Clausen <lars@metafoo.de>
66 return -EINVAL; in axi_spdif_trigger()
69 regmap_update_bits(spdif->regmap, AXI_SPDIF_REG_CTRL, in axi_spdif_trigger()
80 unsigned int clkdiv, stat; in axi_spdif_hw_params() local
97 clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(spdif->clk_ref), in axi_spdif_hw_params()
98 rate * 64 * 2) - 1; in axi_spdif_hw_params()
99 clkdiv <<= AXI_SPDIF_CTRL_CLKDIV_OFFSET; in axi_spdif_hw_params()
101 regmap_write(spdif->regmap, AXI_SPDIF_REG_STAT, stat); in axi_spdif_hw_params()
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/openbmc/u-boot/drivers/w1/
H A Dmxc_w1.c1 // SPDX-License-Identifier: GPL-2.0+
30 #define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
59 u16 *ctrl_addr = &pdata->regs->control; in mxc_w1_touch_bit()
67 while (timeout_cnt--) { in mxc_w1_touch_bit()
80 struct mxc_w1_regs *regs = pdata->regs; in mxc_w1_read_byte()
93 readw(&regs->tx_rx); in mxc_w1_read_byte()
94 writew(0xFF, &regs->tx_rx); in mxc_w1_read_byte()
98 status = readw(&regs->interrupt); in mxc_w1_read_byte()
101 return (u8)readw(&regs->tx_rx); in mxc_w1_read_byte()
107 struct mxc_w1_regs *regs = pdata->regs; in mxc_w1_write_byte()
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dadau1701.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
100 #define ADAU1707_CLKDIV_UNSET (-1U)
192 size = adau1701_register_size(&client->dev, reg); in adau1701_reg_write()
194 return -EINVAL; in adau1701_reg_write()
199 for (i = size + 1; i >= 2; --i) { in adau1701_reg_write()
210 return -EIO; in adau1701_reg_write()
223 size = adau1701_register_size(&client->dev, reg); in adau1701_reg_read()
225 return -EINVAL; in adau1701_reg_read()
230 msgs[0].addr = client->addr; in adau1701_reg_read()
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/openbmc/u-boot/drivers/clk/
H A Dclk_stm32mp1.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
7 #include <clk-uclass.h>
15 #include <dt-bindings/clock/stm32mp1-clks.h>
16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
745 (u32)priv->osc[idx], priv->osc[idx] / 1000); in stm32mp1_clk_get_fixed()
747 return priv->osc[idx]; in stm32mp1_clk_get_fixed()
752 const struct stm32mp1_clk_gate *gate = priv->data->gate; in stm32mp1_clk_get_id()
753 int i, nb_clks = priv->data->nb_gate; in stm32mp1_clk_get_id()
762 return -EINVAL; in stm32mp1_clk_get_id()
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/openbmc/u-boot/board/freescale/mpc8548cds/
H A Dmpc8548cds.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
53 gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ in checkboard()
55 ecm->eedr = 0xffffffff; /* clear ecm errors */ in checkboard()
56 ecm->eeer = 0xffffffff; /* enable ecm errors */ in checkboard()
69 uint clkdiv; in local_bus_init() local
73 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; in local_bus_init()
75 gur->lbiuiplldcr1 = 0x00078080; in local_bus_init()
76 if (clkdiv == 16) { in local_bus_init()
77 gur->lbiuiplldcr0 = 0x7c0f1bf0; in local_bus_init()
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/openbmc/linux/drivers/iio/adc/
H A Dlpc18xx_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * - Hardware triggers
9 * - Burst mode
10 * - Interrupts
11 * - DMA
74 reg = adc->cr_reg | BIT(ch) | LPC18XX_ADC_CR_START_NOW; in lpc18xx_adc_read_chan()
75 writel(reg, adc->base + LPC18XX_ADC_CR); in lpc18xx_adc_read_chan()
77 ret = readl_poll_timeout(adc->base + LPC18XX_ADC_GDR, reg, in lpc18xx_adc_read_chan()
80 dev_warn(adc->dev, "adc read timed out\n"); in lpc18xx_adc_read_chan()
95 mutex_lock(&adc->lock); in lpc18xx_adc_read_raw()
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/openbmc/u-boot/board/freescale/mpc8568mds/
H A Dmpc8568mds.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
108 port_c->cpdir2 |= 0x0f000000; in board_early_init_f()
109 port_c->cppar2 &= ~0x0f000000; in board_early_init_f()
110 port_c->cppar2 |= 0x0a000000; in board_early_init_f()
132 uint clkdiv; in local_bus_init() local
136 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; in local_bus_init()
138 gur->lbiuiplldcr1 = 0x00078080; in local_bus_init()
139 if (clkdiv == 16) { in local_bus_init()
140 gur->lbiuiplldcr0 = 0x7c0f1bf0; in local_bus_init()
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/openbmc/qemu/tests/qtest/
H A Dnpcm7xx_adc-test.c100 return qtest_readl(qts, adc->base_addr + CON_OFFSET); in adc_read_con()
105 qtest_writel(qts, adc->base_addr + CON_OFFSET, value); in adc_write_con()
110 return qtest_readl(qts, adc->base_addr + DATA_OFFSET); in adc_read_data()
115 return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0]) in adc_calibrate()
116 / (int32_t)(rv[1] - rv[0]); in adc_calibrate()
127 response = qtest_qmp(qts, "{ 'execute': 'qom-set'," in adc_qom_set()
170 uint32_t clkdiv) in adc_calculate_steps() argument
172 return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale; in adc_calculate_steps()
176 uint32_t clkdiv) in adc_wait_conv_finished() argument
185 clkdiv)); in adc_wait_conv_finished()
[all …]
/openbmc/linux/drivers/gpu/drm/exynos/
H A Dexynos7_drm_decon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
30 #include "regs-decon7.h"
62 {.compatible = "samsung,exynos7-decon"},
86 struct decon_context *ctx = crtc->ctx; in decon_wait_for_vblank()
88 if (ctx->suspended) in decon_wait_for_vblank()
91 atomic_set(&ctx->wait_vsync_event, 1); in decon_wait_for_vblank()
97 if (!wait_event_timeout(ctx->wait_vsync_queue, in decon_wait_for_vblank()
98 !atomic_read(&ctx->wait_vsync_event), in decon_wait_for_vblank()
100 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); in decon_wait_for_vblank()
105 struct decon_context *ctx = crtc->ctx; in decon_clear_channels()
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/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dlpc32xx_nand_mlc.c1 // SPDX-License-Identifier: GPL-2.0+
10 * The MLC NAND flash controller provides hardware Reed-Solomon ECC
11 * covering in- and out-of-band data together. Therefore, in- and out-
12 * of-band data must be written together in order to have a valid ECC.
14 * Consequently, pages with meaningful in-band data are written with
15 * blank (all-ones) out-of-band data and a valid ECC, and any later
16 * out-of-band data write will void the ECC.
18 * Therefore, code which reads such late-written out-of-band data
62 #define ICR_ADDR4 0x00000002 /* configure for 4-word addrs */
75 /* time-out for NAND chip / controller loops, in us */
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