drivers/mmc/gen_atmel_mci.c

1 // SPDX-License-Identifier: GPL-2.0+
5  * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de>
8  * Copyright (C) 2004-2006 Atmel Corporation
59 	return readl(&mci->version) & 0x00000fff;  in atmel_mci_get_version()
65  * - always when DEBUG is defined
66  * - on command errors
82 		writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->blkr)),  in mci_set_blklen()
83 		       &mci->blkr);  in mci_set_blklen()
85 		writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->mr)), &mci->mr);  in mci_set_blklen()
94 	struct mmc *mmc = &plat->mmc;
95 	u32 bus_hz = priv->bus_clk_rate;
96 	atmel_mci_t *mci = plat->mci;
100 	struct atmel_mci_priv *priv = mmc->priv;
102 	atmel_mci_t *mci = priv->mci;
105 	u32 clkdiv = 255;  local
114 			clkdiv = DIV_ROUND_UP(bus_hz, hz) - 2;
115 			if (clkdiv > 511)
116 				clkdiv = 511;
118 			clkodd = clkdiv & 1;
119 			clkdiv >>= 1;
122 			      bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
124 			/* find clkdiv yielding a rate <= than requested */
125 			for (clkdiv = 0; clkdiv < 255; clkdiv++) {
126 				if ((bus_hz / (clkdiv + 1) / 2) <= hz)
130 			      (bus_hz / (clkdiv + 1)) / 2, blklen);
135 		priv->curr_clk = bus_hz / (clkdiv * 2 + clkodd + 2);
137 		priv->curr_clk = (bus_hz / (clkdiv + 1)) / 2;
139 	mr = MMCI_BF(CLKDIV, clkdiv);
152 	writel(mr, &mci->mr);
156 	if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS)
157 		writel(MMCI_BIT(HSMODE), &mci->cfg);
159 	priv->initialized = 1;
177 		if (data->blocks > 1)
179 		if (data->flags & MMC_DATA_READ)
183 	if (cmd->resp_type & MMC_RSP_CRC)
185 	if (cmd->resp_type & MMC_RSP_136)
187 	else if (cmd->resp_type & MMC_RSP_BUSY)
189 	else if (cmd->resp_type & MMC_RSP_PRESENT)
192 	return cmdr | MMCI_BF(CMDNB, cmd->cmdidx);
201 		status = readl(&mci->sr);
207 		*data = readl(&mci->rdr);
220 		status = readl(&mci->sr);
226 		writel(*data, &mci->tdr);
245 	atmel_mci_t *mci = plat->mci;
250 	struct atmel_mci_priv *priv = mmc->priv;
251 	atmel_mci_t *mci = priv->mci;
257 	if (!priv->initialized) {
259 		return -ECOMM;
265 	mci_set_blklen(mci, data->blocksize);
268 	if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
269 			|| (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
270 		writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize),
271 		       &mci->blkr);
274 	writel(cmd->cmdarg, &mci->argr);
275 	writel(cmdr, &mci->cmdr);
278 	dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG");
282 	while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY)));
285 		dump_cmd(cmdr, cmd->cmdarg, status, "Command Time Out");
286 		return -ETIMEDOUT;
288 		dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed");
289 		return -ECOMM;
293 	if (cmd->resp_type & MMC_RSP_136) {
294 		cmd->response[0] = readl(&mci->rspr);
295 		cmd->response[1] = readl(&mci->rspr1);
296 		cmd->response[2] = readl(&mci->rspr2);
297 		cmd->response[3] = readl(&mci->rspr3);
299 		cmd->response[0] = readl(&mci->rspr);
309 		if (data->flags & MMC_DATA_READ) {
311 			ioptr = (u32*)data->dest;
314 			ioptr = (u32*)data->src;
319 				block_count < data->blocks && !status;
326 			} while (!status && word_count < (data->blocksize/4));
328 			if (data->flags & MMC_DATA_READ)
332 				print_buffer(0, data->dest + cnt * block_count,
337 				dump_cmd(cmdr, cmd->cmdarg, status,
339 				return -ECOMM;
346 			status = readl(&mci->sr);
349 				dump_cmd(cmdr, cmd->cmdarg, status,
351 				return -ECOMM;
356 			dump_cmd(cmdr, cmd->cmdarg, status,
365 	if (cmd->cmdidx == MMC_CMD_SWITCH)
366 		udelay(8*1000000 / priv->curr_clk); /* 8 clk in us */
376 	atmel_mci_t *mci = plat->mci;
381 	struct atmel_mci_priv *priv = mmc->priv;
382 	atmel_mci_t *mci = priv->mci;
384 	int bus_width = mmc->bus_width;
390 	mci_set_mode(dev, mmc->clock, MMC_DEFAULT_BLKLEN);
392 	mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);
412 		writel(busw << 6 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
416 		writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
426 	atmel_mci_t *mci = plat->mci;
431 	struct atmel_mci_priv *priv = mmc->priv;
432 	atmel_mci_t *mci = priv->mci;
436 	writel(MMCI_BIT(SWRST), &mci->cr);	/* soft reset */
437 	writel(MMCI_BIT(PWSDIS), &mci->cr);	/* disable power save */
438 	writel(MMCI_BIT(MCIEN), &mci->cr);	/* enable mci */
439 	writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);	/* select port */
442 	writel(0x7f, &mci->dtor);
444 	writel(~0UL, &mci->idr);
477 		return -ENOMEM;
479 	cfg = &priv->cfg;
481 	cfg->name = "mci";
482 	cfg->ops = &atmel_mci_ops;
484 	priv->mci = (struct atmel_mci *)regs;
485 	priv->initialized = 0;
488 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
489 	version = atmel_mci_get_version(priv->mci);
491 		cfg->host_caps = MMC_MODE_8BIT;
492 		cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
495 	cfg->host_caps |= MMC_MODE_4BIT;
501 	cfg->f_min = get_mci_clk_rate() / (2*256);
502 	cfg->f_max = get_mci_clk_rate() / (2*1);
504 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
510 		return -ENODEV;
531 	cfg = &plat->cfg;
532 	cfg->name = "Atmel mci";
533 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
536 	 * If the version is above 3.0, the capabilities of the 8-bit
539 	version = atmel_mci_get_version(plat->mci);
541 		cfg->host_caps = MMC_MODE_8BIT |
545 	cfg->host_caps |= MMC_MODE_4BIT;
546 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
547 	cfg->f_min = priv->bus_clk_rate / (2 * 256);
548 	cfg->f_max = priv->bus_clk_rate / 2;
560 		ret = -EINVAL;
570 		ret = -EINVAL;
574 	priv->bus_clk_rate = clk_rate;
593 	plat->mci = (struct atmel_mci *)devfdt_get_addr_ptr(dev);
597 	mmc = &plat->mmc;
598 	mmc->cfg = &plat->cfg;
599 	mmc->dev = dev;
600 	upriv->mmc = mmc;
611 	return mmc_bind(dev, &plat->mmc, &plat->cfg);
620 	.name = "atmel-mci",