Home
last modified time | relevance | path

Searched full:arcv2 (Results 1 – 25 of 42) sorted by relevance

12

/openbmc/linux/arch/arc/include/asm/
H A Darcregs.h10 #define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
11 #define ARC_REG_ERP_CTRL 0x3F /* ARCv2 Error protection control */
18 #define ARC_REG_ERP_BUILD 0xc7 /* ARCv2 Error protection Build: ECC/Parity */
19 #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
34 #define ARC_REG_LPB_BUILD 0xE9 /* ARCv2 Loop Buffer Build */
37 #define ARC_REG_MICRO_ARCH_BCR 0xF9 /* ARCv2 Product revision */
40 #define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */
41 #define ARC_REG_LPB_CTRL 0x488 /* ARCv2 Loop Buffer control */
45 /* Common for ARCompact and ARCv2 status register */
H A Dfpu.h28 * ARCv2 FPU Control aux register
32 * ARCv2 FPU Status aux register
H A Dirqflags.h13 #include <asm/irqflags-arcv2.h>
H A Dmmu.h21 #include <asm/mmu-arcv2.h>
H A Dirq.h10 * ARCv2 can support 240 interrupts in the core interrupts controllers and
H A Datomic.h31 #include <asm/atomic64-arcv2.h>
H A Dpgtable.h12 #include <asm/pgtable-bits-arcv2.h>
H A Dbarrier.h12 * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
H A Dentry-arcv2.h8 #include <asm/irqflags-arcv2.h>
12 * Interrupt/Exception stack layout (pt_regs) for ARCv2
H A Dspinlock.h37 * ARCv2 only has load-load, store-store and all-all barrier in arch_spin_lock()
266 * RELEASE barrier: given the instructions avail on ARCv2, full barrier in arch_spin_unlock()
H A Dcache.h56 * ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit
/openbmc/linux/arch/arc/kernel/
H A DMakefile11 obj-$(CONFIG_ISA_ARCV2) += entry-arcv2.o intc-arcv2.o
H A Dentry-arcv2.S3 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
168 ;############# Common Handlers for ARCompact and ARCv2 ##############
172 ;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ##############
229 ; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
H A Dintc-arcv2.c59 * ARCv2 core intc provides multiple interrupt priorities (upto 16). in arc_init_IRQ()
126 .name = "ARCv2 core Intc",
H A Dmcip.c13 #include <asm/irqflags-arcv2.h>
181 * ARCv2 Interrupt Distribution Unit (IDU)
298 * ARCv2 IDU HW does not support inverse polarity, so these are the in idu_irq_set_type()
H A Djump_label.c38 * ARCv2 'Branch unconditionally' instruction:
/openbmc/u-boot/arch/arc/include/asm/
H A Darcregs.h51 #define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */
52 #define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
/openbmc/u-boot/arch/arc/lib/
H A Dcache.c642 * ARCv2 && L1 D$ disabled -> nothing in invalidate_dcache_range()
643 * ARCv2 && L1 D$ enabled && IOC enabled -> nothing in invalidate_dcache_range()
644 * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op in invalidate_dcache_range()
660 * ARCv2 && L1 D$ disabled -> nothing in flush_dcache_range()
661 * ARCv2 && L1 D$ enabled && IOC enabled -> nothing in flush_dcache_range()
662 * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op in flush_dcache_range()
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsnps,archs-intc.txt1 * ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)
/openbmc/linux/arch/arc/lib/
H A Dmemcpy-archs-unaligned.S3 * ARCv2 memcpy implementation optimized for unaligned memory access using.
H A Dmemcmp.S25 /* In ARCv2 a branch can't be the last instruction in a zero overhead
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Damlogic,meson-mx-ao-arc.yaml13 ISA, while Meson8, Meson8b and Meson8m2 use an ARC EM4 (ARCv2 ISA)
/openbmc/linux/drivers/clocksource/
H A Darc_timer.c11 * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
154 .name = "ARCv2 RTC",
/openbmc/u-boot/arch/arc/
H A DKconfig9 default "arcv2" if ISA_ARCV2
/openbmc/linux/include/uapi/linux/
H A Delf-em.h50 #define EM_ARCV2 195 /* ARCv2 Cores */

12