1d2912cb1SThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 21f6ccfffSVineet Gupta/* 31f6ccfffSVineet Gupta * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling 41f6ccfffSVineet Gupta * 51f6ccfffSVineet Gupta * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) 61f6ccfffSVineet Gupta */ 71f6ccfffSVineet Gupta 81f6ccfffSVineet Gupta#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */ 91f6ccfffSVineet Gupta#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */ 101f6ccfffSVineet Gupta#include <asm/errno.h> 111f6ccfffSVineet Gupta#include <asm/arcregs.h> 121f6ccfffSVineet Gupta#include <asm/irqflags.h> 13*a79a9c76SVineet Gupta#include <asm/mmu.h> 141f6ccfffSVineet Gupta 15f33b8cddSYuriy Kolerov; A maximum number of supported interrupts in the core interrupt controller. 16f33b8cddSYuriy Kolerov; This number is not equal to the maximum interrupt number (256) because 17f33b8cddSYuriy Kolerov; first 16 lines are reserved for exceptions and are not configurable. 18f33b8cddSYuriy Kolerov#define NR_CPU_IRQS 240 19f33b8cddSYuriy Kolerov 201f6ccfffSVineet Gupta .cpu HS 211f6ccfffSVineet Gupta 221f6ccfffSVineet Gupta#define VECTOR .word 231f6ccfffSVineet Gupta 241f6ccfffSVineet Gupta;############################ Vector Table ################################# 251f6ccfffSVineet Gupta 261f6ccfffSVineet Gupta .section .vector,"a",@progbits 271f6ccfffSVineet Gupta .align 4 281f6ccfffSVineet Gupta 291f6ccfffSVineet Gupta# Initial 16 slots are Exception Vectors 303971cdc2SVineet GuptaVECTOR res_service ; Reset Vector 311f6ccfffSVineet GuptaVECTOR mem_service ; Mem exception 321f6ccfffSVineet GuptaVECTOR instr_service ; Instrn Error 331f6ccfffSVineet GuptaVECTOR EV_MachineCheck ; Fatal Machine check 341f6ccfffSVineet GuptaVECTOR EV_TLBMissI ; Intruction TLB miss 351f6ccfffSVineet GuptaVECTOR EV_TLBMissD ; Data TLB miss 361f6ccfffSVineet GuptaVECTOR EV_TLBProtV ; Protection Violation 371f6ccfffSVineet GuptaVECTOR EV_PrivilegeV ; Privilege Violation 381f6ccfffSVineet GuptaVECTOR EV_SWI ; Software Breakpoint 391f6ccfffSVineet GuptaVECTOR EV_Trap ; Trap exception 401f6ccfffSVineet GuptaVECTOR EV_Extension ; Extn Instruction Exception 411f6ccfffSVineet GuptaVECTOR EV_DivZero ; Divide by Zero 421f6ccfffSVineet GuptaVECTOR EV_DCError ; Data Cache Error 431f6ccfffSVineet GuptaVECTOR EV_Misaligned ; Misaligned Data Access 441f6ccfffSVineet GuptaVECTOR reserved ; Reserved slots 451f6ccfffSVineet GuptaVECTOR reserved ; Reserved slots 461f6ccfffSVineet Gupta 471f6ccfffSVineet Gupta# Begin Interrupt Vectors 481f6ccfffSVineet GuptaVECTOR handle_interrupt ; (16) Timer0 491f6ccfffSVineet GuptaVECTOR handle_interrupt ; unused (Timer1) 501f6ccfffSVineet GuptaVECTOR handle_interrupt ; unused (WDT) 51bb143f81SVineet GuptaVECTOR handle_interrupt ; (19) Inter core Interrupt (IPI) 52bb143f81SVineet GuptaVECTOR handle_interrupt ; (20) perf Interrupt 53bb143f81SVineet GuptaVECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI) 54bb143f81SVineet GuptaVECTOR handle_interrupt ; unused 55bb143f81SVineet GuptaVECTOR handle_interrupt ; (23) unused 56bb143f81SVineet Gupta# End of fixed IRQs 571f6ccfffSVineet Gupta 58f33b8cddSYuriy Kolerov.rept NR_CPU_IRQS - 8 591f6ccfffSVineet Gupta VECTOR handle_interrupt 601f6ccfffSVineet Gupta.endr 611f6ccfffSVineet Gupta 621f6ccfffSVineet Gupta .section .text, "ax",@progbits 631f6ccfffSVineet Gupta 643d592659SVineet Guptareserved: 653d592659SVineet Gupta flag 1 ; Unexpected event, halt 661f6ccfffSVineet Gupta 671f6ccfffSVineet Gupta;##################### Interrupt Handling ############################## 681f6ccfffSVineet Gupta 691f6ccfffSVineet GuptaENTRY(handle_interrupt) 701f6ccfffSVineet Gupta 71a4880801SVineet Gupta INTERRUPT_PROLOGUE 721f6ccfffSVineet Gupta 7378833e79SVineet Gupta # irq control APIs local_irq_save/restore/disable/enable fiddle with 7478833e79SVineet Gupta # global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio) 7578833e79SVineet Gupta # However a taken interrupt doesn't clear these bits. Thus irqs_disabled() 7678833e79SVineet Gupta # query in hard ISR path would return false (since .IE is set) which would 7778833e79SVineet Gupta # trips genirq interrupt handling asserts. 7878833e79SVineet Gupta # 7978833e79SVineet Gupta # So do a "soft" disable of interrutps here. 8078833e79SVineet Gupta # 8178833e79SVineet Gupta # Note this disable is only for consistent book-keeping as further interrupts 8278833e79SVineet Gupta # will be disabled anyways even w/o this. Hardware tracks active interrupts 8375370ad4SVineet Gupta # seperately in AUX_IRQ_ACT.active and will not take new interrupts 8478833e79SVineet Gupta # unless this one returns (or higher prio becomes pending in 2-prio scheme) 851f6ccfffSVineet Gupta 8678833e79SVineet Gupta IRQ_DISABLE 871f6ccfffSVineet Gupta 8878833e79SVineet Gupta ; icause is banked: one per priority level 8978833e79SVineet Gupta ; so a higher prio interrupt taken here won't clobber prev prio icause 90d9676fa1SEvgeny Voevodin lr r0, [ICAUSE] 911f6ccfffSVineet Gupta mov blink, ret_from_exception 921f6ccfffSVineet Gupta 931f6ccfffSVineet Gupta b.d arch_do_IRQ 941f6ccfffSVineet Gupta mov r1, sp 951f6ccfffSVineet Gupta 961f6ccfffSVineet GuptaEND(handle_interrupt) 971f6ccfffSVineet Gupta 981f6ccfffSVineet Gupta;################### Non TLB Exception Handling ############################# 991f6ccfffSVineet Gupta 1001f6ccfffSVineet GuptaENTRY(EV_SWI) 101814a5850SVineet Gupta ; TODO: implement this 102814a5850SVineet Gupta EXCEPTION_PROLOGUE 103814a5850SVineet Gupta b ret_from_exception 1041f6ccfffSVineet GuptaEND(EV_SWI) 1051f6ccfffSVineet Gupta 1061f6ccfffSVineet GuptaENTRY(EV_DivZero) 107814a5850SVineet Gupta ; TODO: implement this 108814a5850SVineet Gupta EXCEPTION_PROLOGUE 109814a5850SVineet Gupta b ret_from_exception 1101f6ccfffSVineet GuptaEND(EV_DivZero) 1111f6ccfffSVineet Gupta 1121f6ccfffSVineet GuptaENTRY(EV_DCError) 113814a5850SVineet Gupta ; TODO: implement this 114814a5850SVineet Gupta EXCEPTION_PROLOGUE 115814a5850SVineet Gupta b ret_from_exception 1161f6ccfffSVineet GuptaEND(EV_DCError) 1171f6ccfffSVineet Gupta 118541366daSVineet Gupta; --------------------------------------------- 119541366daSVineet Gupta; Memory Error Exception Handler 120541366daSVineet Gupta; - Unlike ARCompact, handles Bus errors for both User/Kernel mode, 121541366daSVineet Gupta; Instruction fetch or Data access, under a single Exception Vector 122541366daSVineet Gupta; --------------------------------------------- 123541366daSVineet Gupta 124541366daSVineet GuptaENTRY(mem_service) 125541366daSVineet Gupta 126541366daSVineet Gupta EXCEPTION_PROLOGUE 127541366daSVineet Gupta 128541366daSVineet Gupta bl do_memory_error 129541366daSVineet Gupta b ret_from_exception 130541366daSVineet GuptaEND(mem_service) 131541366daSVineet Gupta 1321f6ccfffSVineet GuptaENTRY(EV_Misaligned) 1331f6ccfffSVineet Gupta 1341f6ccfffSVineet Gupta EXCEPTION_PROLOGUE 1351f6ccfffSVineet Gupta 1361f6ccfffSVineet Gupta SAVE_CALLEE_SAVED_USER 1371f6ccfffSVineet Gupta mov r2, sp ; callee_regs 1381f6ccfffSVineet Gupta 1391f6ccfffSVineet Gupta bl do_misaligned_access 1401f6ccfffSVineet Gupta 1411f6ccfffSVineet Gupta ; TBD: optimize - do this only if a callee reg was involved 1421f6ccfffSVineet Gupta ; either a dst of emulated LD/ST or src with address-writeback 1431f6ccfffSVineet Gupta RESTORE_CALLEE_SAVED_USER 1441f6ccfffSVineet Gupta 1451f6ccfffSVineet Gupta b ret_from_exception 1461f6ccfffSVineet GuptaEND(EV_Misaligned) 1471f6ccfffSVineet Gupta 1481f6ccfffSVineet Gupta; --------------------------------------------- 1491f6ccfffSVineet Gupta; Protection Violation Exception Handler 1501f6ccfffSVineet Gupta; --------------------------------------------- 1511f6ccfffSVineet Gupta 1521f6ccfffSVineet GuptaENTRY(EV_TLBProtV) 1531f6ccfffSVineet Gupta 1541f6ccfffSVineet Gupta EXCEPTION_PROLOGUE 1551f6ccfffSVineet Gupta 1561f6ccfffSVineet Gupta mov blink, ret_from_exception 1571f6ccfffSVineet Gupta b do_page_fault 1581f6ccfffSVineet Gupta 1591f6ccfffSVineet GuptaEND(EV_TLBProtV) 1601f6ccfffSVineet Gupta 1611f6ccfffSVineet Gupta; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they 1621f6ccfffSVineet Gupta; need to call do_page_fault(). 1631f6ccfffSVineet Gupta; ECR in pt_regs provides whether access was R/W/X 1641f6ccfffSVineet Gupta 1651f6ccfffSVineet Gupta.global call_do_page_fault 1661f6ccfffSVineet Gupta.set call_do_page_fault, EV_TLBProtV 1671f6ccfffSVineet Gupta 1681f6ccfffSVineet Gupta;############# Common Handlers for ARCompact and ARCv2 ############## 1691f6ccfffSVineet Gupta 1701f6ccfffSVineet Gupta#include "entry.S" 1711f6ccfffSVineet Gupta 1721f6ccfffSVineet Gupta;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ############## 1731f6ccfffSVineet Gupta; 1741f6ccfffSVineet Gupta; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap) 1751f6ccfffSVineet Gupta; IRQ shd definitely not happen between now and rtie 1761f6ccfffSVineet Gupta; All 2 entry points to here already disable interrupts 1771f6ccfffSVineet Gupta 1781f6ccfffSVineet Gupta.Lrestore_regs: 17978833e79SVineet Guptarestore_regs: 1801f6ccfffSVineet Gupta 181d9676fa1SEvgeny Voevodin # Interrpts are actually disabled from this point on, but will get 182d9676fa1SEvgeny Voevodin # reenabled after we return from interrupt/exception. 183d9676fa1SEvgeny Voevodin # But irq tracer needs to be told now... 184d9676fa1SEvgeny Voevodin TRACE_ASM_IRQ_ENABLE 185d9676fa1SEvgeny Voevodin 1861f6ccfffSVineet Gupta ld r0, [sp, PT_status32] ; U/K mode at time of entry 1871f6ccfffSVineet Gupta lr r10, [AUX_IRQ_ACT] 1881f6ccfffSVineet Gupta 18975370ad4SVineet Gupta bmsk r11, r10, 15 ; extract AUX_IRQ_ACT.active 1901f6ccfffSVineet Gupta breq r11, 0, .Lexcept_ret ; No intr active, ret from Exception 1911f6ccfffSVineet Gupta 1921f6ccfffSVineet Gupta;####### Return from Intr ####### 1931f6ccfffSVineet Gupta 19475370ad4SVineet Gupta.Lisr_ret: 19575370ad4SVineet Gupta 1961f6ccfffSVineet Guptadebug_marker_l1: 197e494239aSVineet Gupta ; bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot 198e494239aSVineet Gupta btst r0, STATUS_DE_BIT ; Z flag set if bit clear 199e494239aSVineet Gupta bnz .Lintr_ret_to_delay_slot ; branch if STATUS_DE_BIT set 2004255b07fSVineet Gupta 2011f6ccfffSVineet Gupta ; Handle special case #1: (Entry via Exception, Return via IRQ) 2021f6ccfffSVineet Gupta ; 2031f6ccfffSVineet Gupta ; Exception in U mode, preempted in kernel, Intr taken (K mode), orig 2041f6ccfffSVineet Gupta ; task now returning to U mode (riding the Intr) 2051f6ccfffSVineet Gupta ; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP 2061f6ccfffSVineet Gupta ; won't be switched to correct U mode value (from AUX_SP) 2071f6ccfffSVineet Gupta ; So force AUX_IRQ_ACT.U for such a case 2081f6ccfffSVineet Gupta 2091f6ccfffSVineet Gupta btst r0, STATUS_U_BIT ; Z flag set if K (Z clear for U) 2101f6ccfffSVineet Gupta bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U 2111f6ccfffSVineet Gupta sr r11, [AUX_IRQ_ACT] 2121f6ccfffSVineet Gupta 213a4880801SVineet Gupta INTERRUPT_EPILOGUE 2141f6ccfffSVineet Gupta rtie 2151f6ccfffSVineet Gupta 2161f6ccfffSVineet Gupta;####### Return from Exception / pure kernel mode ####### 2171f6ccfffSVineet Gupta 2181f6ccfffSVineet Gupta.Lexcept_ret: ; Expects r0 has PT_status32 2191f6ccfffSVineet Gupta 2201f6ccfffSVineet Guptadebug_marker_syscall: 2211f6ccfffSVineet Gupta EXCEPTION_EPILOGUE 2221f6ccfffSVineet Gupta rtie 2231f6ccfffSVineet Gupta 2244255b07fSVineet Gupta;####### Return from Intr to insn in delay slot ####### 2254255b07fSVineet Gupta 2264255b07fSVineet Gupta; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ) 2274255b07fSVineet Gupta; 2284255b07fSVineet Gupta; Intr returning to a Delay Slot (DS) insn 2294255b07fSVineet Gupta; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig 2304255b07fSVineet Gupta; entry was via Exception in DS which got preempted in kernel). 2314255b07fSVineet Gupta; 232cbfe74a7SVineet Gupta; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround 233cbfe74a7SVineet Gupta; 23475370ad4SVineet Gupta; Solution is to drop out of interrupt context into pure kernel mode 23575370ad4SVineet Gupta; and return from pure kernel mode which does right things for delay slot 236cbfe74a7SVineet Gupta 2374255b07fSVineet Gupta.Lintr_ret_to_delay_slot: 2384255b07fSVineet Guptadebug_marker_ds: 2394255b07fSVineet Gupta 2404255b07fSVineet Gupta ld r2, [@intr_to_DE_cnt] 2414255b07fSVineet Gupta add r2, r2, 1 2424255b07fSVineet Gupta st r2, [@intr_to_DE_cnt] 2434255b07fSVineet Gupta 24475370ad4SVineet Gupta ; drop out of interrupt context (clear AUX_IRQ_ACT.active) 24575370ad4SVineet Gupta bmskn r11, r10, 15 24675370ad4SVineet Gupta sr r11, [AUX_IRQ_ACT] 24775370ad4SVineet Gupta b .Lexcept_ret 2484255b07fSVineet Gupta 2491f6ccfffSVineet GuptaEND(ret_from_exception) 250