1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2ac4c244dSVineet Gupta /*
3ac4c244dSVineet Gupta * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4ac4c244dSVineet Gupta */
5ac4c244dSVineet Gupta
6ac4c244dSVineet Gupta #ifndef _ASM_ARC_ARCREGS_H
7ac4c244dSVineet Gupta #define _ASM_ARC_ARCREGS_H
8ac4c244dSVineet Gupta
9bacdf480SVineet Gupta /* Build Configuration Registers */
10a150b085SVineet Gupta #define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
11f3156851SVineet Gupta #define ARC_REG_ERP_CTRL 0x3F /* ARCv2 Error protection control */
12a150b085SVineet Gupta #define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */
13af617428SVineet Gupta #define ARC_REG_CRC_BCR 0x62
14bacdf480SVineet Gupta #define ARC_REG_VECBASE_BCR 0x68
15af617428SVineet Gupta #define ARC_REG_PERIBASE_BCR 0x69
1656372082SVineet Gupta #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
1756372082SVineet Gupta #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
18f3156851SVineet Gupta #define ARC_REG_ERP_BUILD 0xc7 /* ARCv2 Error protection Build: ECC/Parity */
191f6ccfffSVineet Gupta #define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
20d1f317d8SVineet Gupta #define ARC_REG_SLC_BCR 0xce
21a150b085SVineet Gupta #define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */
2256372082SVineet Gupta #define ARC_REG_AP_BCR 0x76
23a150b085SVineet Gupta #define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */
24af617428SVineet Gupta #define ARC_REG_XY_MEM_BCR 0x79
25af617428SVineet Gupta #define ARC_REG_MAC_BCR 0x7a
26*fad84e39SVineet Gupta #define ARC_REG_MPY_BCR 0x7b
27af617428SVineet Gupta #define ARC_REG_SWAP_BCR 0x7c
28af617428SVineet Gupta #define ARC_REG_NORM_BCR 0x7d
29af617428SVineet Gupta #define ARC_REG_MIXMAX_BCR 0x7e
30af617428SVineet Gupta #define ARC_REG_BARREL_BCR 0x7f
31af617428SVineet Gupta #define ARC_REG_D_UNCACH_BCR 0x6A
3256372082SVineet Gupta #define ARC_REG_BPU_BCR 0xc0
3356372082SVineet Gupta #define ARC_REG_ISA_CFG_BCR 0xc1
34f3156851SVineet Gupta #define ARC_REG_LPB_BUILD 0xE9 /* ARCv2 Loop Buffer Build */
35a44ec8bdSVineet Gupta #define ARC_REG_RTT_BCR 0xF2
36820970a5SVineet Gupta #define ARC_REG_IRQ_BCR 0xF3
37f3156851SVineet Gupta #define ARC_REG_MICRO_ARCH_BCR 0xF9 /* ARCv2 Product revision */
3856372082SVineet Gupta #define ARC_REG_SMART_BCR 0xFF
39f2b0b25aSAlexey Brodkin #define ARC_REG_CLUSTER_BCR 0xcf
40a150b085SVineet Gupta #define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */
41f3156851SVineet Gupta #define ARC_REG_LPB_CTRL 0x488 /* ARCv2 Loop Buffer control */
42f45ba2bdSVineet Gupta #define ARC_REG_FPU_CTRL 0x300
43f45ba2bdSVineet Gupta #define ARC_REG_FPU_STATUS 0x301
44bacdf480SVineet Gupta
45e98a7bf0SYuriy Kolerov /* Common for ARCompact and ARCv2 status register */
46e98a7bf0SYuriy Kolerov #define ARC_REG_STATUS32 0x0A
47e98a7bf0SYuriy Kolerov
48ac4c244dSVineet Gupta /* status32 Bits Positions */
49ac4c244dSVineet Gupta #define STATUS_AE_BIT 5 /* Exception active */
50ac4c244dSVineet Gupta #define STATUS_DE_BIT 6 /* PC is in delay slot */
51ac4c244dSVineet Gupta #define STATUS_U_BIT 7 /* User/Kernel mode */
52e6e335bfSVineet Gupta #define STATUS_Z_BIT 11
53ac4c244dSVineet Gupta #define STATUS_L_BIT 12 /* Loop inhibit */
54ac4c244dSVineet Gupta
55ac4c244dSVineet Gupta /* These masks correspond to the status word(STATUS_32) bits */
56ac4c244dSVineet Gupta #define STATUS_AE_MASK (1<<STATUS_AE_BIT)
57ac4c244dSVineet Gupta #define STATUS_DE_MASK (1<<STATUS_DE_BIT)
58ac4c244dSVineet Gupta #define STATUS_U_MASK (1<<STATUS_U_BIT)
59e6e335bfSVineet Gupta #define STATUS_Z_MASK (1<<STATUS_Z_BIT)
60ac4c244dSVineet Gupta #define STATUS_L_MASK (1<<STATUS_L_BIT)
61ac4c244dSVineet Gupta
62cc562d2eSVineet Gupta /*
63cc562d2eSVineet Gupta * ECR: Exception Cause Reg bits-n-pieces
64cc562d2eSVineet Gupta * [23:16] = Exception Vector
65cc562d2eSVineet Gupta * [15: 8] = Exception Cause Code
66cc562d2eSVineet Gupta * [ 7: 0] = Exception Parameters (for certain types only)
67cc562d2eSVineet Gupta */
681f6ccfffSVineet Gupta #ifdef CONFIG_ISA_ARCOMPACT
69dc9e234fSVineet Gupta #define ECR_V_MEM_ERR 0x01
70cc562d2eSVineet Gupta #define ECR_V_INSN_ERR 0x02
71cc562d2eSVineet Gupta #define ECR_V_MACH_CHK 0x20
72cc562d2eSVineet Gupta #define ECR_V_ITLB_MISS 0x21
73cc562d2eSVineet Gupta #define ECR_V_DTLB_MISS 0x22
74cc562d2eSVineet Gupta #define ECR_V_PROTV 0x23
75502a0c77SVineet Gupta #define ECR_V_TRAP 0x25
761f6ccfffSVineet Gupta #else
771f6ccfffSVineet Gupta #define ECR_V_MEM_ERR 0x01
781f6ccfffSVineet Gupta #define ECR_V_INSN_ERR 0x02
791f6ccfffSVineet Gupta #define ECR_V_MACH_CHK 0x03
801f6ccfffSVineet Gupta #define ECR_V_ITLB_MISS 0x04
811f6ccfffSVineet Gupta #define ECR_V_DTLB_MISS 0x05
821f6ccfffSVineet Gupta #define ECR_V_PROTV 0x06
831f6ccfffSVineet Gupta #define ECR_V_TRAP 0x09
8476551468SEugeniy Paltsev #define ECR_V_MISALIGN 0x0d
851f6ccfffSVineet Gupta #endif
86cc562d2eSVineet Gupta
87dc9e234fSVineet Gupta /* DTLB Miss and Protection Violation Cause Codes */
88dc9e234fSVineet Gupta
89cc562d2eSVineet Gupta #define ECR_C_PROTV_INST_FETCH 0x00
90cc562d2eSVineet Gupta #define ECR_C_PROTV_LOAD 0x01
91cc562d2eSVineet Gupta #define ECR_C_PROTV_STORE 0x02
92cc562d2eSVineet Gupta #define ECR_C_PROTV_XCHG 0x03
93cc562d2eSVineet Gupta #define ECR_C_PROTV_MISALIG_DATA 0x04
94cc562d2eSVineet Gupta
951898a959SVineet Gupta #define ECR_C_BIT_PROTV_MISALIG_DATA 10
961898a959SVineet Gupta
971898a959SVineet Gupta /* Machine Check Cause Code Values */
981898a959SVineet Gupta #define ECR_C_MCHK_DUP_TLB 0x01
991898a959SVineet Gupta
100cc562d2eSVineet Gupta /* DTLB Miss Exception Cause Code Values */
101cc562d2eSVineet Gupta #define ECR_C_BIT_DTLB_LD_MISS 8
102cc562d2eSVineet Gupta #define ECR_C_BIT_DTLB_ST_MISS 9
103cc562d2eSVineet Gupta
104ac4c244dSVineet Gupta /* Auxiliary registers */
105ac4c244dSVineet Gupta #define AUX_IDENTITY 4
106dea82520SVineet Gupta #define AUX_EXEC_CTRL 8
107ac4c244dSVineet Gupta #define AUX_INTR_VEC_BASE 0x25
10826c01c49SVineet Gupta #define AUX_VOL 0x5e
109f1f3347dSVineet Gupta
110bf90e1eaSVineet Gupta /*
111bf90e1eaSVineet Gupta * Floating Pt Registers
112bf90e1eaSVineet Gupta * Status regs are read-only (build-time) so need not be saved/restored
113bf90e1eaSVineet Gupta */
114bf90e1eaSVineet Gupta #define ARC_AUX_FP_STAT 0x300
115bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_1L 0x301
116bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_1H 0x302
117bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_2L 0x303
118bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_2H 0x304
119bf90e1eaSVineet Gupta #define ARC_AUX_DPFP_STAT 0x305
120bf90e1eaSVineet Gupta
1214827d0cfSEugeniy Paltsev /*
1224827d0cfSEugeniy Paltsev * DSP-related registers
1237321e2eaSEugeniy Paltsev * Registers names must correspond to dsp_callee_regs structure fields names
1247321e2eaSEugeniy Paltsev * for automatic offset calculation in DSP_AUX_SAVE_RESTORE macros.
1254827d0cfSEugeniy Paltsev */
1264827d0cfSEugeniy Paltsev #define ARC_AUX_DSP_BUILD 0x7A
1274827d0cfSEugeniy Paltsev #define ARC_AUX_ACC0_LO 0x580
1284827d0cfSEugeniy Paltsev #define ARC_AUX_ACC0_GLO 0x581
1294827d0cfSEugeniy Paltsev #define ARC_AUX_ACC0_HI 0x582
1304827d0cfSEugeniy Paltsev #define ARC_AUX_ACC0_GHI 0x583
1314827d0cfSEugeniy Paltsev #define ARC_AUX_DSP_BFLY0 0x598
1324827d0cfSEugeniy Paltsev #define ARC_AUX_DSP_CTRL 0x59F
1334827d0cfSEugeniy Paltsev #define ARC_AUX_DSP_FFT_CTRL 0x59E
1344827d0cfSEugeniy Paltsev
135f09d3174SEugeniy Paltsev #define ARC_AUX_AGU_BUILD 0xCC
136f09d3174SEugeniy Paltsev #define ARC_AUX_AGU_AP0 0x5C0
137f09d3174SEugeniy Paltsev #define ARC_AUX_AGU_AP1 0x5C1
138f09d3174SEugeniy Paltsev #define ARC_AUX_AGU_AP2 0x5C2
139f09d3174SEugeniy Paltsev #define ARC_AUX_AGU_AP3 0x5C3
140f09d3174SEugeniy Paltsev #define ARC_AUX_AGU_OS0 0x5D0
141f09d3174SEugeniy Paltsev #define ARC_AUX_AGU_OS1 0x5D1
142f09d3174SEugeniy Paltsev #define ARC_AUX_AGU_MOD0 0x5E0
143f09d3174SEugeniy Paltsev #define ARC_AUX_AGU_MOD1 0x5E1
144f09d3174SEugeniy Paltsev #define ARC_AUX_AGU_MOD2 0x5E2
145f09d3174SEugeniy Paltsev #define ARC_AUX_AGU_MOD3 0x5E3
146f09d3174SEugeniy Paltsev
147ac4c244dSVineet Gupta #ifndef __ASSEMBLY__
148ac4c244dSVineet Gupta
149c33a605dSVineet Gupta #include <soc/arc/aux.h>
15095d6976dSVineet Gupta
151c121c506SVineet Gupta /* Helpers */
152c121c506SVineet Gupta #define TO_KB(bytes) ((bytes) >> 10)
153c121c506SVineet Gupta #define TO_MB(bytes) (TO_KB(bytes) >> 10)
154c121c506SVineet Gupta #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
155c121c506SVineet Gupta #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
15695d6976dSVineet Gupta
157bf90e1eaSVineet Gupta
15895d6976dSVineet Gupta /*
15995d6976dSVineet Gupta ***************************************************************
16095d6976dSVineet Gupta * Build Configuration Registers, with encoded hardware config
16195d6976dSVineet Gupta */
162af617428SVineet Gupta struct bcr_identity {
163af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
164af617428SVineet Gupta unsigned int chip_id:16, cpu_id:8, family:8;
165af617428SVineet Gupta #else
166af617428SVineet Gupta unsigned int family:8, cpu_id:8, chip_id:16;
167af617428SVineet Gupta #endif
168af617428SVineet Gupta };
16995d6976dSVineet Gupta
170010a8c98SVineet Gupta struct bcr_isa_arcv2 {
171af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
1721f6ccfffSVineet Gupta unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
173010a8c98SVineet Gupta pad1:12, ver:8;
174af617428SVineet Gupta #else
175010a8c98SVineet Gupta unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
1761f6ccfffSVineet Gupta ldd:1, pad2:4, div_rem:4;
177af617428SVineet Gupta #endif
178af617428SVineet Gupta };
179af617428SVineet Gupta
180*fad84e39SVineet Gupta struct bcr_uarch_build {
1817b2e932fSVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
1827b2e932fSVineet Gupta unsigned int pad:8, prod:8, maj:8, min:8;
1837b2e932fSVineet Gupta #else
1847b2e932fSVineet Gupta unsigned int min:8, maj:8, prod:8, pad:8;
1857b2e932fSVineet Gupta #endif
1867b2e932fSVineet Gupta };
1877b2e932fSVineet Gupta
18872d861f2SVineet Gupta struct bcr_mmu_3 {
18972d861f2SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
19072d861f2SVineet Gupta unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,
19172d861f2SVineet Gupta u_itlb:4, u_dtlb:4;
19272d861f2SVineet Gupta #else
19372d861f2SVineet Gupta unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4,
19472d861f2SVineet Gupta ways:4, ver:8;
19572d861f2SVineet Gupta #endif
19672d861f2SVineet Gupta };
19772d861f2SVineet Gupta
19872d861f2SVineet Gupta struct bcr_mmu_4 {
19972d861f2SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
20072d861f2SVineet Gupta unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
20172d861f2SVineet Gupta n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
20272d861f2SVineet Gupta #else
20372d861f2SVineet Gupta /* DTLB ITLB JES JE JA */
20472d861f2SVineet Gupta unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
20572d861f2SVineet Gupta pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
20672d861f2SVineet Gupta #endif
20772d861f2SVineet Gupta };
20872d861f2SVineet Gupta
20917a5ed56SVineet Gupta struct bcr_cache {
21017a5ed56SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
21117a5ed56SVineet Gupta unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
21217a5ed56SVineet Gupta #else
21317a5ed56SVineet Gupta unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
21417a5ed56SVineet Gupta #endif
21517a5ed56SVineet Gupta };
21617a5ed56SVineet Gupta
21717a5ed56SVineet Gupta struct bcr_slc_cfg {
21817a5ed56SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
21917a5ed56SVineet Gupta unsigned int pad:24, way:2, lsz:2, sz:4;
22017a5ed56SVineet Gupta #else
22117a5ed56SVineet Gupta unsigned int sz:4, lsz:2, way:2, pad:24;
22217a5ed56SVineet Gupta #endif
22317a5ed56SVineet Gupta };
22417a5ed56SVineet Gupta
22517a5ed56SVineet Gupta struct bcr_clust_cfg {
22617a5ed56SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
22717a5ed56SVineet Gupta unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
22817a5ed56SVineet Gupta #else
22917a5ed56SVineet Gupta unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
23017a5ed56SVineet Gupta #endif
23117a5ed56SVineet Gupta };
23217a5ed56SVineet Gupta
23317a5ed56SVineet Gupta struct bcr_volatile {
23417a5ed56SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
23517a5ed56SVineet Gupta unsigned int start:4, limit:4, pad:22, order:1, disable:1;
23617a5ed56SVineet Gupta #else
23717a5ed56SVineet Gupta unsigned int disable:1, order:1, pad:22, limit:4, start:4;
23817a5ed56SVineet Gupta #endif
23917a5ed56SVineet Gupta };
24017a5ed56SVineet Gupta
24156372082SVineet Gupta struct bcr_mpy {
242af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
24356372082SVineet Gupta unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
244af617428SVineet Gupta #else
24556372082SVineet Gupta unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
246af617428SVineet Gupta #endif
247af617428SVineet Gupta };
248af617428SVineet Gupta
249a150b085SVineet Gupta struct bcr_iccm_arcompact {
250af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
251af617428SVineet Gupta unsigned int base:16, pad:5, sz:3, ver:8;
252af617428SVineet Gupta #else
253af617428SVineet Gupta unsigned int ver:8, sz:3, pad:5, base:16;
254af617428SVineet Gupta #endif
255af617428SVineet Gupta };
256af617428SVineet Gupta
257a150b085SVineet Gupta struct bcr_iccm_arcv2 {
258af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
259a150b085SVineet Gupta unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
260af617428SVineet Gupta #else
261a150b085SVineet Gupta unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
262af617428SVineet Gupta #endif
263af617428SVineet Gupta };
264af617428SVineet Gupta
265a150b085SVineet Gupta struct bcr_dccm_arcompact {
266af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
267af617428SVineet Gupta unsigned int res:21, sz:3, ver:8;
268af617428SVineet Gupta #else
269af617428SVineet Gupta unsigned int ver:8, sz:3, res:21;
270af617428SVineet Gupta #endif
271af617428SVineet Gupta };
272af617428SVineet Gupta
273a150b085SVineet Gupta struct bcr_dccm_arcv2 {
274a150b085SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
275a150b085SVineet Gupta unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
276a150b085SVineet Gupta #else
277a150b085SVineet Gupta unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
278a150b085SVineet Gupta #endif
279a150b085SVineet Gupta };
280a150b085SVineet Gupta
28156372082SVineet Gupta /* ARCompact: Both SP and DP FPU BCRs have same format */
28256372082SVineet Gupta struct bcr_fp_arcompact {
283af617428SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
284af617428SVineet Gupta unsigned int fast:1, ver:8;
285af617428SVineet Gupta #else
286af617428SVineet Gupta unsigned int ver:8, fast:1;
287af617428SVineet Gupta #endif
288af617428SVineet Gupta };
289af617428SVineet Gupta
2901f6ccfffSVineet Gupta struct bcr_fp_arcv2 {
2911f6ccfffSVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
2921f6ccfffSVineet Gupta unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
2931f6ccfffSVineet Gupta #else
2941f6ccfffSVineet Gupta unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
2951f6ccfffSVineet Gupta #endif
2961f6ccfffSVineet Gupta };
2971f6ccfffSVineet Gupta
2987dd380c3SVineet Gupta struct bcr_actionpoint {
2997dd380c3SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
3007dd380c3SVineet Gupta unsigned int pad:21, min:1, num:2, ver:8;
3017dd380c3SVineet Gupta #else
3027dd380c3SVineet Gupta unsigned int ver:8, num:2, min:1, pad:21;
3037dd380c3SVineet Gupta #endif
3047dd380c3SVineet Gupta };
3057dd380c3SVineet Gupta
306b26c2e38SVineet Gupta #include <soc/arc/timers.h>
30756372082SVineet Gupta
30856372082SVineet Gupta struct bcr_bpu_arcompact {
30956372082SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
31056372082SVineet Gupta unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
31156372082SVineet Gupta #else
31256372082SVineet Gupta unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
31356372082SVineet Gupta #endif
31456372082SVineet Gupta };
31556372082SVineet Gupta
3161f6ccfffSVineet Gupta struct bcr_bpu_arcv2 {
3171f6ccfffSVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
3181f6ccfffSVineet Gupta unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
3191f6ccfffSVineet Gupta #else
3201f6ccfffSVineet Gupta unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
3211f6ccfffSVineet Gupta #endif
3221f6ccfffSVineet Gupta };
3231f6ccfffSVineet Gupta
324f3156851SVineet Gupta /* Error Protection Build: ECC/Parity */
325f3156851SVineet Gupta struct bcr_erp {
326f3156851SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
327f3156851SVineet Gupta unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8;
328f3156851SVineet Gupta #else
329f3156851SVineet Gupta unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5;
330f3156851SVineet Gupta #endif
331f3156851SVineet Gupta };
332f3156851SVineet Gupta
333f3156851SVineet Gupta /* Error Protection Control */
334f3156851SVineet Gupta struct ctl_erp {
335f3156851SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
336f3156851SVineet Gupta unsigned int pad2:27, mpd:1, pad1:2, dpd:1, dpi:1;
337f3156851SVineet Gupta #else
338f3156851SVineet Gupta unsigned int dpi:1, dpd:1, pad1:2, mpd:1, pad2:27;
339f3156851SVineet Gupta #endif
340f3156851SVineet Gupta };
341f3156851SVineet Gupta
342f3156851SVineet Gupta struct bcr_lpb {
343f3156851SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
344f3156851SVineet Gupta unsigned int pad:16, entries:8, ver:8;
345f3156851SVineet Gupta #else
346f3156851SVineet Gupta unsigned int ver:8, entries:8, pad:16;
347f3156851SVineet Gupta #endif
348f3156851SVineet Gupta };
349f3156851SVineet Gupta
35056372082SVineet Gupta struct bcr_generic {
35156372082SVineet Gupta #ifdef CONFIG_CPU_BIG_ENDIAN
352a150b085SVineet Gupta unsigned int info:24, ver:8;
35356372082SVineet Gupta #else
354a150b085SVineet Gupta unsigned int ver:8, info:24;
35556372082SVineet Gupta #endif
35656372082SVineet Gupta };
35756372082SVineet Gupta
is_isa_arcv2(void)3581f6ccfffSVineet Gupta static inline int is_isa_arcv2(void)
3591f6ccfffSVineet Gupta {
3601f6ccfffSVineet Gupta return IS_ENABLED(CONFIG_ISA_ARCV2);
3611f6ccfffSVineet Gupta }
3621f6ccfffSVineet Gupta
is_isa_arcompact(void)3631f6ccfffSVineet Gupta static inline int is_isa_arcompact(void)
3641f6ccfffSVineet Gupta {
3651f6ccfffSVineet Gupta return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
3661f6ccfffSVineet Gupta }
3671f6ccfffSVineet Gupta
368ac4c244dSVineet Gupta #endif /* __ASEMBLY__ */
369ac4c244dSVineet Gupta
370ac4c244dSVineet Gupta #endif /* _ASM_ARC_ARCREGS_H */
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