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/openbmc/u-boot/drivers/sound/
H A Dmax98090.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * max98090.h -- MAX98090 ALSA SoC Audio driver
66 /* MAX98090 Registers Bit Fields */
71 #define M98090_SWRESET_MASK BIT(7)
76 #define M98090_SR_96K_MASK BIT(5)
77 #define M98090_SR_96K_SHIFT 5
79 #define M98090_SR_32K_MASK BIT(4)
82 #define M98090_SR_48K_MASK BIT(3)
85 #define M98090_SR_44K1_MASK BIT(2)
88 #define M98090_SR_16K_MASK BIT(1)
[all …]
/openbmc/linux/include/linux/mfd/da9062/
H A Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2015-2017 Dialog Semiconductor
151 * Bit fields
158 #define DA9062AA_WRITE_MODE_MASK BIT(6)
160 #define DA9062AA_REVERT_MASK BIT(7)
166 #define DA9062AA_DVC_BUSY_MASK BIT(2)
172 #define DA9062AA_GPI1_MASK BIT(1)
174 #define DA9062AA_GPI2_MASK BIT(2)
176 #define DA9062AA_GPI3_MASK BIT(3)
178 #define DA9062AA_GPI4_MASK BIT(4)
[all …]
/openbmc/linux/drivers/usb/typec/tcpm/
H A Dfusb302_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2017 Google, Inc
5 * Fairchild FUSB302 Type-C Chip Driver
13 #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7)
14 #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6)
15 #define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5)
16 #define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4)
17 #define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3)
18 #define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2)
19 #define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1)
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/openbmc/linux/Documentation/input/devices/
H A Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
22 5. Hardware version 2
25 5.2.1 Parity checking and packet re-synchronization
58 4 allows tracking up to 5 fingers.
114 non-zero value will turn it ON. For hardware version 1 the default is ON.
118 calculating a parity bit for the last 3 bytes of each packet. The driver
145 4 bytes version: (after the arrow is the name given in the Dell-provided driver)
173 ---------
179 echo -n 0x16 > reg_10
183 bit 7 6 5 4 3 2 1 0
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/openbmc/linux/drivers/net/dsa/microchip/
H A Dksz8795_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
22 #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4)
23 #define KSZ8863_PCS_RESET BIT(0)
27 #define SW_NEW_BACKOFF BIT(7)
28 #define SW_GLOBAL_RESET BIT(6)
29 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)
30 #define SW_FLUSH_STA_MAC_TABLE BIT(4)
31 #define SW_LINK_AUTO_AGING BIT(0)
35 #define SW_HUGE_PACKET BIT(6)
36 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)
[all …]
H A Dksz9477_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 Microchip Technology Inc.
14 /* 0 - Operation */
43 #define PME_ENABLE BIT(1)
44 #define PME_POLARITY BIT(0)
48 #define SW_GIGABIT_ABLE BIT(6)
49 #define SW_REDUNDANCY_ABLE BIT(5)
50 #define SW_AVB_ABLE BIT(4)
68 #define SW_QW_ABLE BIT(5)
74 #define LUE_INT BIT(31)
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/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
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H A Dkwbimage_128M16_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
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/openbmc/linux/sound/soc/codecs/
H A Drk3328_codec.h1 /* SPDX-License-Identifier: GPL-2.0 */
37 #define PIN_DIRECTION_MASK BIT(5)
38 #define PIN_DIRECTION_IN (0x0 << 5)
39 #define PIN_DIRECTION_OUT (0x1 << 5)
40 #define DAC_I2S_MODE_MASK BIT(4)
45 #define DAC_I2S_LRP_MASK BIT(7)
48 #define DAC_VDL_MASK GENMASK(6, 5)
49 #define DAC_VDL_16BITS (0x0 << 5)
50 #define DAC_VDL_20BITS (0x1 << 5)
51 #define DAC_VDL_24BITS (0x2 << 5)
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/openbmc/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix-i2c-txcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
27 #define SP_REGISTER_PD BIT(7)
28 #define SP_HDCP_PD BIT(5)
29 #define SP_AUDIO_PD BIT(4)
30 #define SP_VIDEO_PD BIT(3)
31 #define SP_LINK_PD BIT(2)
32 #define SP_TOTAL_PD BIT(1)
36 #define SP_MISC_RST BIT(7)
37 #define SP_VIDCAP_RST BIT(6)
38 #define SP_VIDFIF_RST BIT(5)
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/openbmc/linux/include/linux/mfd/
H A Dtps65219.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
90 #define TPS65219_REG_INT_RV_POS 5
102 #define TPS65219_BUCKS_LDOS_VOUT_VSET_MASK GENMASK(5, 0)
103 #define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6)
104 #define TPS65219_BUCKS_BW_SEL_MASK BIT(7)
106 #define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT)
107 #define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7)
109 #define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0)
110 #define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1)
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H A Dtps6594.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
236 #define TPS6594_BIT_BUCK_EN BIT(0)
237 #define TPS6594_BIT_BUCK_FPWM BIT(1)
238 #define TPS6594_BIT_BUCK_FPWM_MP BIT(2)
239 #define TPS6594_BIT_BUCK_VSEL BIT(3)
240 #define TPS6594_BIT_BUCK_VMON_EN BIT(4)
241 #define TPS6594_BIT_BUCK_PLDN BIT(5)
242 #define TPS6594_BIT_BUCK_RV_SEL BIT(7)
246 #define TPS6594_MASK_BUCK_ILIM GENMASK(5, 3)
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H A Drohm-bd71815.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 * Author: yanglsh@embest-tech.com
32 /* LDO for Low-Power State Retention */
236 #define BD71815_BUCK_PWM_FIXED BIT(4)
237 #define BD71815_BUCK_SNVS_ON BIT(3)
238 #define BD71815_BUCK_RUN_ON BIT(2)
239 #define BD71815_BUCK_LPSR_ON BIT(1)
240 #define BD71815_BUCK_SUSP_ON BIT(0)
243 #define BD71815_BUCK_DVSSEL BIT(7)
244 #define BD71815_BUCK_STBY_DVS BIT(6)
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H A Dtps65218.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
63 #define TPS65218_INT1_VPRG BIT(5)
64 #define TPS65218_INT1_AC BIT(4)
65 #define TPS65218_INT1_PB BIT(3)
66 #define TPS65218_INT1_HOT BIT(2)
67 #define TPS65218_INT1_CC_AQC BIT(1)
68 #define TPS65218_INT1_PRGC BIT(0)
70 #define TPS65218_INT2_LS3_F BIT(5)
71 #define TPS65218_INT2_LS2_F BIT(4)
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/openbmc/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddpkg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2015 Freescale Semiconductor Inc.
16 * DPKG_NUM_OF_MASKS - Number of masks per key extraction
21 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
26 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
38 * enum dpkg_extract_type - Enumeration for selecting extraction type
41 * @DPKG_EXTRACT_FROM_PARSE: Extract from parser-result;
52 * struct dpkg_mask - A structure for defining a single extraction mask
64 #define NH_FLD_ETH_DA BIT(0)
65 #define NH_FLD_ETH_SA BIT(1)
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/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_SWC_CLEAR_IF BIT(6)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(5)
23 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(4)
24 #define ICPU_GENERAL_CTRL_IF_MASTER_DIS BIT(3)
25 #define ICPU_GENERAL_CTRL_IF_MASTER_SPI_ENA BIT(2)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10)
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/openbmc/linux/drivers/platform/x86/intel/pmc/
H A Dmtl.c1 // SPDX-License-Identifier: GPL-2.0
17 * MTL-M SOC-M IOE-M None
18 * MTL-P SOC-M IOE-P None
19 * MTL-S SOC-S IOE-P PCH-S
23 {"PMC", BIT(0)},
24 {"OPI", BIT(1)},
25 {"SPI", BIT(2)},
26 {"XHCI", BIT(3)},
27 {"SPA", BIT(4)},
28 {"SPB", BIT(5)},
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/openbmc/linux/drivers/gpu/drm/mcde/
H A Dmcde_dsi_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1)
10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2)
11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3)
12 #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4)
13 #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5)
14 #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6)
15 #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7)
16 #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8)
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/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10)
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/openbmc/qemu/target/avr/
H A Dinsn.decode4 # Copyright (c) 2019-2020 Michael Rolnik <mrolnik@gmail.com>
26 %rd 4:5
66 COM 1001 010 rd:5 0000
67 NEG 1001 010 rd:5 0001
68 INC 1001 010 rd:5 0011
69 DEC 1001 010 rd:5 1010
82 # The 22-bit immediate is partially in the opcode word,
84 # complete 22-bit value.
85 %imm_call 4:5 0:1 !function=append_16
87 @op_bit .... .... . bit:3 ....
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/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
28 /* n = 0,1,2,3,4,5 */
40 #define TCU_TCSR_PWM_SD BIT(9)
41 #define TCU_TCSR_PWM_INITL_HIGH BIT(8)
42 #define TCU_TCSR_PWM_EN BIT(7)
51 #define TCU_TCSR_EXT_EN BIT(2)
52 #define TCU_TCSR_RTC_EN BIT(1)
53 #define TCU_TCSR_PCK_EN BIT(0)
55 #define TCU_TER_TCEN5 BIT(5)
56 #define TCU_TER_TCEN4 BIT(4)
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/openbmc/linux/include/linux/soundwire/
H A Dsdw_registers.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
36 #define SDW_DP0_INT_TEST_FAIL BIT(0)
37 #define SDW_DP0_INT_PORT_READY BIT(1)
38 #define SDW_DP0_INT_BRA_FAILURE BIT(2)
39 #define SDW_DP0_SDCA_CASCADE BIT(3)
40 /* BIT(4) not allocated in SoundWire specification 1.2 */
41 #define SDW_DP0_INT_IMPDEF1 BIT(5)
42 #define SDW_DP0_INT_IMPDEF2 BIT(6)
43 #define SDW_DP0_INT_IMPDEF3 BIT(7)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(11)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(10)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(9)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(8)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(7)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(15)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(14)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(13)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(12)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(11)
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