Lines Matching +full:5 +full:- +full:bit
1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
30 # bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged
31 # bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged
32 # bit 12-8: 3, MPPSel10 UA0_TXD
33 # bit 15-12: 3, MPPSel11 UA0_RXD
34 # bit 19-16: 0, MPPSel12 not connected
35 # bit 23-20: 3, MPPSel13 GPIO[14]
36 # bit 27-24: 3, MPPSel14 GPIO[15]
37 # bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
40 # bit 3-0: 0, MPPSel16 GPIO[16]
41 # bit 7-4: 0, MPPSel17 not connected
42 # bit 11-8: 1, MPPSel18 NF_IO[0]
43 # bit 15-12: 1, MPPSel19 NF_IO[1]
44 # bit 19-16: 0, MPPSel20 GPIO[20]
45 # bit 23-20: 0, MPPSel21 GPIO[21]
46 # bit 27-24: 0, MPPSel22 GPIO[22]
47 # bit 31-28: 0, MPPSel23 GPIO[23]
49 # MPP Control 3-6 Register untouched (MPP24-49)
52 # bit 2-0: 3, Reserved
53 # bit 5-3: 3, Reserved
54 # bit 6: 0, Reserved
55 # bit 7: 0, RGMII-pads voltage = 3.3V
56 # bit 10-8: 3, Reserved
57 # bit 13-11: 3, Reserved
58 # bit 14: 0, Reserved
59 # bit 15: 0, MPP RGMII-pads voltage = 3.3V
60 # bit 31-16 0x1B1B, Reserved
63 # bit 0-1: 2, Tag RAM RTC RAM0
64 # bit 3-2: 1, Tag RAM WTC RAM0
65 # bit 7-4: 6, Reserved
66 # bit 9-8: 2, Valid RAM RTC RAM
67 # bit 11-10: 1, Valid RAM WTC RAM
68 # bit 13-12: 2, Dirty RAM RTC RAM
69 # bit 15-14: 1, Dirty RAM WTC RAM
70 # bit 17-16: 2, Data RAM RTC RAM0
71 # bit 19-18: 1, Data RAM WTC RAM0
72 # bit 21-20: 2, Data RAM RTC RAM1
73 # bit 23-22: 1, Data RAM WTC RAM1
74 # bit 25-24: 2, Data RAM RTC RAM2
75 # bit 27-26: 1, Data RAM WTC RAM2
76 # bit 29-28: 2, Data RAM RTC RAM3
77 # bit 31-30: 1, Data RAM WTC RAM4
80 # bit 15-0: ?, Reserved
81 # bit 17-16: 2, ECC RAM RTC RAM0
82 # bit 19-18: 1, ECC RAM WTC RAM0
83 # bit 31-20: ?,Reserved
90 # bit 13-0: 0x4E0, DDR2 clks refresh rate
91 # bit 14: 0, reserved
92 # bit 15: 0, reserved
93 # bit 16: 0, CPU to Dram Write buffer policy
94 # bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic
95 # bit 19-18: 0, reserved
96 # bit 23-20: 0, reserved
97 # bit 24: 1, enable exit self refresh mode on DDR access
98 # bit 25: 1, required
99 # bit 29-26: 0, reserved
100 # bit 31-30: 1, reserved
103 # bit 3-0: 0, reserved
104 # bit 4: 0, 2T mode =addr/cmd in same cycle
105 # bit 5: 0, clk is driven during self refresh, we don't care for APX
106 # bit 6: 0, use recommended falling edge of clk for addr/cmd
107 # bit 7-11: 0, reserved
108 # bit 12-13: 1, reserved, required 1
109 # bit 14: 0, input buffer always powered up
110 # bit 17-15: 0, reserved
111 # bit 18: 1, cpu lock transaction enabled
112 # bit 19: 0, reserved
113 # bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
114 # bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM
115 # bit 30-28: 3, required
116 # bit 31: 0, no additional STARTBURST delay
119 # bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles
120 # bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles
121 # bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles
122 # bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
123 # bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
124 # bit 20: 0, extended TRAS msb
125 # bit 23-21: 0, reserved
126 # bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
127 # bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
130 # bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles
131 # bit 8-7: 0, TR2R
132 # bit 10-9: 0, TR2W
133 # bit 12-11: 0, TW2W
134 # bit 31-13: 0, reserved
137 # bit 1-0: 0, Cs0width=x8 (2 devices)
138 # bit 3-2: 0, Cs0size=2Gb
139 # bit 5-4: 0, Cs1width=nonexistent
140 # bit 7-6: 0, Cs1size =nonexistent
141 # bit 9-8: 0, Cs2width=nonexistent
142 # bit 11-10: 0, Cs2size =nonexistent
143 # bit 13-12: 0, Cs3width=nonexistent
144 # bit 15-14: 0, Cs3size =nonexistent
145 # bit 16: 0, Cs0AddrSel
146 # bit 17: 0, Cs1AddrSel
147 # bit 18: 0, Cs2AddrSel
148 # bit 19: 0, Cs3AddrSel
149 # bit 31-20: 0, required
152 # bit 0: 0, OpenPage enabled
153 # bit 31-1: 0, required
156 # bit 3-0: 0, DDR cmd
157 # bit 31-4: 0, required
160 # bit 2-0: 2, Burst Length = 4
161 # bit 3: 0, Burst Type
162 # bit 6-4: 5, CAS Latency = 5
163 # bit 7: 0, Test mode
164 # bit 8: 0, DLL Reset
165 # bit 11-9: 3, Write recovery for auto-precharge must be 3
166 # bit 12: 0, Active power down exit time, fast exit
167 # bit 14-13: 0, reserved
168 # bit 31-15: 0, reserved
171 # bit 0: 0, DDR DLL enabled
172 # bit 1: 1, DDR drive strenght reduced
173 # bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0]
174 # bit 5-3: 0, required
175 # bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1]
176 # bit 9-7: 0, required
177 # bit 10: 0, differential DQS enabled
178 # bit 11: 0, required
179 # bit 12: 0, DDR output buffer enabled
180 # bit 31-13: 0 required
183 # bit 2-0: 7, required
184 # bit 3: 1, MBUS Burst Chop disabled
185 # bit 6-4: 7, required
186 # bit 7: 0, reserved
187 # bit 8: 1, add sample stage required for > 266Mhz
188 # bit 9: 0, no half clock cycle addition to dataout
189 # bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
190 # bit 11: 0, 1/4 clock cycle skew disabled for write mesh
191 # bit 15-12:0xf, required
192 # bit 31-16: 0, required
195 # bit 3-0: 0, required
196 # bit 7-4: 2, M_ODT assertion 2 cycles after read start command
197 # bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command
198 # (ODT turn off delay 2,5 clk cycles)
199 # bit 15-12: 4, internal ODT time based on bit 7-4
201 # bit 19-16: 8, internal ODT de-assertion based on bit 11-8
203 # bit 31-20: 0, required
206 # bit 3-0: 2, M_ODT assertion same as bit 11-8
207 # bit 7-4: 5, M_ODT de-assertion same as bit 15-12
208 # bit 11-8: 4, internal ODT assertion 2 cycles after write start command
210 # bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command
214 # bit 23-0: 0, reserved
215 # bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
218 # bit 0: 1, Window enabled
219 # bit 1: 0, Write Protect disabled
220 # bit 3-2: 0, CS0 hit selected
221 # bit 23-4:ones, required
222 # bit 31-24:0x1F, Size (i.e. 512MB)
229 # bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
230 # bit 7-4: 0, ODT0Rd, MODT[1] not asserted
231 # bit 11-8: 0, required
232 # big 15-11: 0, required
233 # bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
234 # bit 23-20: 0, ODT0Wr, MODT[1] not asserted
235 # bit 27-24: 0, required
236 # bit 31-28: 0, required
239 # bit 1-0: 0, ODT0 controlled by ODT Control (low) register above
240 # bit 3-2: 1, ODT1 never active
241 # bit 31-4: 0, required
244 # bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
245 # bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
246 # bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr
247 # bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm
248 # bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm
249 # bit 14: 1, STARTBURST ODT enabled
250 # bit 15: 1, Use ODT Block
253 # bit 0: 1, enable DDR init upon this register write
254 # bit 31-1: 0, reserved