1ad9301a2SIcenowy Zheng /* SPDX-License-Identifier: GPL-2.0-only */ 2ad9301a2SIcenowy Zheng /* 3ad9301a2SIcenowy Zheng * Copyright(c) 2016, Analogix Semiconductor. All rights reserved. 4ad9301a2SIcenowy Zheng */ 5ad9301a2SIcenowy Zheng #ifndef _ANALOGIX_I2C_TXCOMMON_H_ 6ad9301a2SIcenowy Zheng #define _ANALOGIX_I2C_TXCOMMON_H_ 7ad9301a2SIcenowy Zheng 8ad9301a2SIcenowy Zheng /***************************************************************/ 9ad9301a2SIcenowy Zheng /* Register definitions for TX_P2 */ 10ad9301a2SIcenowy Zheng /***************************************************************/ 11ad9301a2SIcenowy Zheng 12ad9301a2SIcenowy Zheng /* 13ad9301a2SIcenowy Zheng * Core Register Definitions 14ad9301a2SIcenowy Zheng */ 15ad9301a2SIcenowy Zheng 16ad9301a2SIcenowy Zheng /* Device ID Low Byte Register */ 17ad9301a2SIcenowy Zheng #define SP_DEVICE_IDL_REG 0x02 18ad9301a2SIcenowy Zheng 19ad9301a2SIcenowy Zheng /* Device ID High Byte Register */ 20ad9301a2SIcenowy Zheng #define SP_DEVICE_IDH_REG 0x03 21ad9301a2SIcenowy Zheng 22ad9301a2SIcenowy Zheng /* Device version register */ 23ad9301a2SIcenowy Zheng #define SP_DEVICE_VERSION_REG 0x04 24ad9301a2SIcenowy Zheng 25ad9301a2SIcenowy Zheng /* Power Down Control Register */ 26ad9301a2SIcenowy Zheng #define SP_POWERDOWN_CTRL_REG 0x05 27ad9301a2SIcenowy Zheng #define SP_REGISTER_PD BIT(7) 28ad9301a2SIcenowy Zheng #define SP_HDCP_PD BIT(5) 29ad9301a2SIcenowy Zheng #define SP_AUDIO_PD BIT(4) 30ad9301a2SIcenowy Zheng #define SP_VIDEO_PD BIT(3) 31ad9301a2SIcenowy Zheng #define SP_LINK_PD BIT(2) 32ad9301a2SIcenowy Zheng #define SP_TOTAL_PD BIT(1) 33ad9301a2SIcenowy Zheng 34ad9301a2SIcenowy Zheng /* Reset Control Register 1 */ 35ad9301a2SIcenowy Zheng #define SP_RESET_CTRL1_REG 0x06 36ad9301a2SIcenowy Zheng #define SP_MISC_RST BIT(7) 37ad9301a2SIcenowy Zheng #define SP_VIDCAP_RST BIT(6) 38ad9301a2SIcenowy Zheng #define SP_VIDFIF_RST BIT(5) 39ad9301a2SIcenowy Zheng #define SP_AUDFIF_RST BIT(4) 40ad9301a2SIcenowy Zheng #define SP_AUDCAP_RST BIT(3) 41ad9301a2SIcenowy Zheng #define SP_HDCP_RST BIT(2) 42ad9301a2SIcenowy Zheng #define SP_SW_RST BIT(1) 43ad9301a2SIcenowy Zheng #define SP_HW_RST BIT(0) 44ad9301a2SIcenowy Zheng 45ad9301a2SIcenowy Zheng /* Reset Control Register 2 */ 46ad9301a2SIcenowy Zheng #define SP_RESET_CTRL2_REG 0x07 47ad9301a2SIcenowy Zheng #define SP_AUX_RST BIT(2) 48ad9301a2SIcenowy Zheng #define SP_SERDES_FIFO_RST BIT(1) 49ad9301a2SIcenowy Zheng #define SP_I2C_REG_RST BIT(0) 50ad9301a2SIcenowy Zheng 51ad9301a2SIcenowy Zheng /* Video Control Register 1 */ 52ad9301a2SIcenowy Zheng #define SP_VID_CTRL1_REG 0x08 53ad9301a2SIcenowy Zheng #define SP_VIDEO_EN BIT(7) 54ad9301a2SIcenowy Zheng #define SP_VIDEO_MUTE BIT(2) 55ad9301a2SIcenowy Zheng #define SP_DE_GEN BIT(1) 56ad9301a2SIcenowy Zheng #define SP_DEMUX BIT(0) 57ad9301a2SIcenowy Zheng 58ad9301a2SIcenowy Zheng /* Video Control Register 2 */ 59ad9301a2SIcenowy Zheng #define SP_VID_CTRL2_REG 0x09 60ad9301a2SIcenowy Zheng #define SP_IN_COLOR_F_MASK 0x03 61ad9301a2SIcenowy Zheng #define SP_IN_YC_BIT_SEL BIT(2) 62ad9301a2SIcenowy Zheng #define SP_IN_BPC_MASK 0x70 63ad9301a2SIcenowy Zheng #define SP_IN_BPC_SHIFT 4 64ad9301a2SIcenowy Zheng # define SP_IN_BPC_12BIT 0x03 65ad9301a2SIcenowy Zheng # define SP_IN_BPC_10BIT 0x02 66ad9301a2SIcenowy Zheng # define SP_IN_BPC_8BIT 0x01 67ad9301a2SIcenowy Zheng # define SP_IN_BPC_6BIT 0x00 68ad9301a2SIcenowy Zheng #define SP_IN_D_RANGE BIT(7) 69ad9301a2SIcenowy Zheng 70ad9301a2SIcenowy Zheng /* Video Control Register 3 */ 71ad9301a2SIcenowy Zheng #define SP_VID_CTRL3_REG 0x0a 72ad9301a2SIcenowy Zheng #define SP_HPD_OUT BIT(6) 73ad9301a2SIcenowy Zheng 74ad9301a2SIcenowy Zheng /* Video Control Register 5 */ 75ad9301a2SIcenowy Zheng #define SP_VID_CTRL5_REG 0x0c 76ad9301a2SIcenowy Zheng #define SP_CSC_STD_SEL BIT(7) 77ad9301a2SIcenowy Zheng #define SP_XVYCC_RNG_LMT BIT(6) 78ad9301a2SIcenowy Zheng #define SP_RANGE_Y2R BIT(5) 79ad9301a2SIcenowy Zheng #define SP_CSPACE_Y2R BIT(4) 80ad9301a2SIcenowy Zheng #define SP_RGB_RNG_LMT BIT(3) 81ad9301a2SIcenowy Zheng #define SP_Y_RNG_LMT BIT(2) 82ad9301a2SIcenowy Zheng #define SP_RANGE_R2Y BIT(1) 83ad9301a2SIcenowy Zheng #define SP_CSPACE_R2Y BIT(0) 84ad9301a2SIcenowy Zheng 85ad9301a2SIcenowy Zheng /* Video Control Register 6 */ 86ad9301a2SIcenowy Zheng #define SP_VID_CTRL6_REG 0x0d 87ad9301a2SIcenowy Zheng #define SP_TEST_PATTERN_EN BIT(7) 88ad9301a2SIcenowy Zheng #define SP_VIDEO_PROCESS_EN BIT(6) 89ad9301a2SIcenowy Zheng #define SP_VID_US_MODE BIT(3) 90ad9301a2SIcenowy Zheng #define SP_VID_DS_MODE BIT(2) 91ad9301a2SIcenowy Zheng #define SP_UP_SAMPLE BIT(1) 92ad9301a2SIcenowy Zheng #define SP_DOWN_SAMPLE BIT(0) 93ad9301a2SIcenowy Zheng 94ad9301a2SIcenowy Zheng /* Video Control Register 8 */ 95ad9301a2SIcenowy Zheng #define SP_VID_CTRL8_REG 0x0f 96ad9301a2SIcenowy Zheng #define SP_VID_VRES_TH BIT(0) 97ad9301a2SIcenowy Zheng 98ad9301a2SIcenowy Zheng /* Total Line Status Low Byte Register */ 99ad9301a2SIcenowy Zheng #define SP_TOTAL_LINE_STAL_REG 0x24 100ad9301a2SIcenowy Zheng 101ad9301a2SIcenowy Zheng /* Total Line Status High Byte Register */ 102ad9301a2SIcenowy Zheng #define SP_TOTAL_LINE_STAH_REG 0x25 103ad9301a2SIcenowy Zheng 104ad9301a2SIcenowy Zheng /* Active Line Status Low Byte Register */ 105ad9301a2SIcenowy Zheng #define SP_ACT_LINE_STAL_REG 0x26 106ad9301a2SIcenowy Zheng 107ad9301a2SIcenowy Zheng /* Active Line Status High Byte Register */ 108ad9301a2SIcenowy Zheng #define SP_ACT_LINE_STAH_REG 0x27 109ad9301a2SIcenowy Zheng 110ad9301a2SIcenowy Zheng /* Vertical Front Porch Status Register */ 111ad9301a2SIcenowy Zheng #define SP_V_F_PORCH_STA_REG 0x28 112ad9301a2SIcenowy Zheng 113ad9301a2SIcenowy Zheng /* Vertical SYNC Width Status Register */ 114ad9301a2SIcenowy Zheng #define SP_V_SYNC_STA_REG 0x29 115ad9301a2SIcenowy Zheng 116ad9301a2SIcenowy Zheng /* Vertical Back Porch Status Register */ 117ad9301a2SIcenowy Zheng #define SP_V_B_PORCH_STA_REG 0x2a 118ad9301a2SIcenowy Zheng 119ad9301a2SIcenowy Zheng /* Total Pixel Status Low Byte Register */ 120ad9301a2SIcenowy Zheng #define SP_TOTAL_PIXEL_STAL_REG 0x2b 121ad9301a2SIcenowy Zheng 122ad9301a2SIcenowy Zheng /* Total Pixel Status High Byte Register */ 123ad9301a2SIcenowy Zheng #define SP_TOTAL_PIXEL_STAH_REG 0x2c 124ad9301a2SIcenowy Zheng 125ad9301a2SIcenowy Zheng /* Active Pixel Status Low Byte Register */ 126ad9301a2SIcenowy Zheng #define SP_ACT_PIXEL_STAL_REG 0x2d 127ad9301a2SIcenowy Zheng 128ad9301a2SIcenowy Zheng /* Active Pixel Status High Byte Register */ 129ad9301a2SIcenowy Zheng #define SP_ACT_PIXEL_STAH_REG 0x2e 130ad9301a2SIcenowy Zheng 131ad9301a2SIcenowy Zheng /* Horizontal Front Porch Status Low Byte Register */ 132ad9301a2SIcenowy Zheng #define SP_H_F_PORCH_STAL_REG 0x2f 133ad9301a2SIcenowy Zheng 134ad9301a2SIcenowy Zheng /* Horizontal Front Porch Statys High Byte Register */ 135ad9301a2SIcenowy Zheng #define SP_H_F_PORCH_STAH_REG 0x30 136ad9301a2SIcenowy Zheng 137ad9301a2SIcenowy Zheng /* Horizontal SYNC Width Status Low Byte Register */ 138ad9301a2SIcenowy Zheng #define SP_H_SYNC_STAL_REG 0x31 139ad9301a2SIcenowy Zheng 140ad9301a2SIcenowy Zheng /* Horizontal SYNC Width Status High Byte Register */ 141ad9301a2SIcenowy Zheng #define SP_H_SYNC_STAH_REG 0x32 142ad9301a2SIcenowy Zheng 143ad9301a2SIcenowy Zheng /* Horizontal Back Porch Status Low Byte Register */ 144ad9301a2SIcenowy Zheng #define SP_H_B_PORCH_STAL_REG 0x33 145ad9301a2SIcenowy Zheng 146ad9301a2SIcenowy Zheng /* Horizontal Back Porch Status High Byte Register */ 147ad9301a2SIcenowy Zheng #define SP_H_B_PORCH_STAH_REG 0x34 148ad9301a2SIcenowy Zheng 149ad9301a2SIcenowy Zheng /* InfoFrame AVI Packet DB1 Register */ 150ad9301a2SIcenowy Zheng #define SP_INFOFRAME_AVI_DB1_REG 0x70 151ad9301a2SIcenowy Zheng 152ad9301a2SIcenowy Zheng /* Bit Control Specific Register */ 153ad9301a2SIcenowy Zheng #define SP_BIT_CTRL_SPECIFIC_REG 0x80 154ad9301a2SIcenowy Zheng #define SP_BIT_CTRL_SELECT_SHIFT 1 155ad9301a2SIcenowy Zheng #define SP_ENABLE_BIT_CTRL BIT(0) 156ad9301a2SIcenowy Zheng 157ad9301a2SIcenowy Zheng /* InfoFrame Audio Packet DB1 Register */ 158ad9301a2SIcenowy Zheng #define SP_INFOFRAME_AUD_DB1_REG 0x83 159ad9301a2SIcenowy Zheng 160ad9301a2SIcenowy Zheng /* InfoFrame MPEG Packet DB1 Register */ 161ad9301a2SIcenowy Zheng #define SP_INFOFRAME_MPEG_DB1_REG 0xb0 162ad9301a2SIcenowy Zheng 163ad9301a2SIcenowy Zheng /* Audio Channel Status Registers */ 164ad9301a2SIcenowy Zheng #define SP_AUD_CH_STATUS_BASE 0xd0 165ad9301a2SIcenowy Zheng 166ad9301a2SIcenowy Zheng /* Audio Channel Num Register 5 */ 167ad9301a2SIcenowy Zheng #define SP_I2S_CHANNEL_NUM_MASK 0xe0 168ad9301a2SIcenowy Zheng # define SP_I2S_CH_NUM_1 (0x00 << 5) 169ad9301a2SIcenowy Zheng # define SP_I2S_CH_NUM_2 (0x01 << 5) 170ad9301a2SIcenowy Zheng # define SP_I2S_CH_NUM_3 (0x02 << 5) 171ad9301a2SIcenowy Zheng # define SP_I2S_CH_NUM_4 (0x03 << 5) 172ad9301a2SIcenowy Zheng # define SP_I2S_CH_NUM_5 (0x04 << 5) 173ad9301a2SIcenowy Zheng # define SP_I2S_CH_NUM_6 (0x05 << 5) 174ad9301a2SIcenowy Zheng # define SP_I2S_CH_NUM_7 (0x06 << 5) 175ad9301a2SIcenowy Zheng # define SP_I2S_CH_NUM_8 (0x07 << 5) 176ad9301a2SIcenowy Zheng #define SP_EXT_VUCP BIT(2) 177ad9301a2SIcenowy Zheng #define SP_VBIT BIT(1) 178ad9301a2SIcenowy Zheng #define SP_AUDIO_LAYOUT BIT(0) 179ad9301a2SIcenowy Zheng 180dea73d61STorsten Duwe /* Analog Debug Register 1 */ 181dea73d61STorsten Duwe #define SP_ANALOG_DEBUG1_REG 0xdc 182dea73d61STorsten Duwe 183ad9301a2SIcenowy Zheng /* Analog Debug Register 2 */ 184ad9301a2SIcenowy Zheng #define SP_ANALOG_DEBUG2_REG 0xdd 185ad9301a2SIcenowy Zheng #define SP_FORCE_SW_OFF_BYPASS 0x20 186ad9301a2SIcenowy Zheng #define SP_XTAL_FRQ 0x1c 187ad9301a2SIcenowy Zheng # define SP_XTAL_FRQ_19M2 (0x00 << 2) 188ad9301a2SIcenowy Zheng # define SP_XTAL_FRQ_24M (0x01 << 2) 189ad9301a2SIcenowy Zheng # define SP_XTAL_FRQ_25M (0x02 << 2) 190ad9301a2SIcenowy Zheng # define SP_XTAL_FRQ_26M (0x03 << 2) 191ad9301a2SIcenowy Zheng # define SP_XTAL_FRQ_27M (0x04 << 2) 192ad9301a2SIcenowy Zheng # define SP_XTAL_FRQ_38M4 (0x05 << 2) 193ad9301a2SIcenowy Zheng # define SP_XTAL_FRQ_52M (0x06 << 2) 194ad9301a2SIcenowy Zheng #define SP_POWERON_TIME_1P5MS 0x03 195ad9301a2SIcenowy Zheng 196ad9301a2SIcenowy Zheng /* Analog Control 0 Register */ 197ad9301a2SIcenowy Zheng #define SP_ANALOG_CTRL0_REG 0xe1 198ad9301a2SIcenowy Zheng 199ad9301a2SIcenowy Zheng /* Common Interrupt Status Register 1 */ 200ad9301a2SIcenowy Zheng #define SP_COMMON_INT_STATUS_BASE (0xf1 - 1) 201ad9301a2SIcenowy Zheng #define SP_PLL_LOCK_CHG 0x40 202ad9301a2SIcenowy Zheng 203ad9301a2SIcenowy Zheng /* Common Interrupt Status Register 2 */ 204ad9301a2SIcenowy Zheng #define SP_COMMON_INT_STATUS2 0xf2 205ad9301a2SIcenowy Zheng #define SP_HDCP_AUTH_CHG BIT(1) 206ad9301a2SIcenowy Zheng #define SP_HDCP_AUTH_DONE BIT(0) 207ad9301a2SIcenowy Zheng 208ad9301a2SIcenowy Zheng #define SP_HDCP_LINK_CHECK_FAIL BIT(0) 209ad9301a2SIcenowy Zheng 210ad9301a2SIcenowy Zheng /* Common Interrupt Status Register 4 */ 211ad9301a2SIcenowy Zheng #define SP_COMMON_INT_STATUS4_REG 0xf4 212ad9301a2SIcenowy Zheng #define SP_HPD_IRQ BIT(6) 213ad9301a2SIcenowy Zheng #define SP_HPD_ESYNC_ERR BIT(4) 214ad9301a2SIcenowy Zheng #define SP_HPD_CHG BIT(2) 215ad9301a2SIcenowy Zheng #define SP_HPD_LOST BIT(1) 216ad9301a2SIcenowy Zheng #define SP_HPD_PLUG BIT(0) 217ad9301a2SIcenowy Zheng 218ad9301a2SIcenowy Zheng /* DP Interrupt Status Register */ 219ad9301a2SIcenowy Zheng #define SP_DP_INT_STATUS1_REG 0xf7 220ad9301a2SIcenowy Zheng #define SP_TRAINING_FINISH BIT(5) 221ad9301a2SIcenowy Zheng #define SP_POLLING_ERR BIT(4) 222ad9301a2SIcenowy Zheng 223ad9301a2SIcenowy Zheng /* Common Interrupt Mask Register */ 224ad9301a2SIcenowy Zheng #define SP_COMMON_INT_MASK_BASE (0xf8 - 1) 225ad9301a2SIcenowy Zheng 226ad9301a2SIcenowy Zheng #define SP_COMMON_INT_MASK4_REG 0xfb 227ad9301a2SIcenowy Zheng 228ad9301a2SIcenowy Zheng /* DP Interrupts Mask Register */ 229ad9301a2SIcenowy Zheng #define SP_DP_INT_MASK1_REG 0xfe 230ad9301a2SIcenowy Zheng 231ad9301a2SIcenowy Zheng /* Interrupt Control Register */ 232ad9301a2SIcenowy Zheng #define SP_INT_CTRL_REG 0xff 233ad9301a2SIcenowy Zheng 234ad9301a2SIcenowy Zheng #endif /* _ANALOGIX_I2C_TXCOMMON_H_ */ 235