1*6bd8231aSGregory CLEMENT /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2*6bd8231aSGregory CLEMENT /* 3*6bd8231aSGregory CLEMENT * Copyright (c) 2018 Microsemi Corporation 4*6bd8231aSGregory CLEMENT */ 5*6bd8231aSGregory CLEMENT 6*6bd8231aSGregory CLEMENT #ifndef _MSCC_OCELOT_ICPU_CFG_H_ 7*6bd8231aSGregory CLEMENT #define _MSCC_OCELOT_ICPU_CFG_H_ 8*6bd8231aSGregory CLEMENT 9*6bd8231aSGregory CLEMENT #define ICPU_GPR(x) (0x4 * (x)) 10*6bd8231aSGregory CLEMENT #define ICPU_GPR_RSZ 0x4 11*6bd8231aSGregory CLEMENT 12*6bd8231aSGregory CLEMENT #define ICPU_RESET 0x20 13*6bd8231aSGregory CLEMENT 14*6bd8231aSGregory CLEMENT #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3) 15*6bd8231aSGregory CLEMENT #define ICPU_RESET_CORE_RST_PROTECT BIT(2) 16*6bd8231aSGregory CLEMENT #define ICPU_RESET_CORE_RST_FORCE BIT(1) 17*6bd8231aSGregory CLEMENT #define ICPU_RESET_MEM_RST_FORCE BIT(0) 18*6bd8231aSGregory CLEMENT 19*6bd8231aSGregory CLEMENT #define ICPU_GENERAL_CTRL 0x24 20*6bd8231aSGregory CLEMENT 21*6bd8231aSGregory CLEMENT #define ICPU_GENERAL_CTRL_SWC_CLEAR_IF BIT(6) 22*6bd8231aSGregory CLEMENT #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(5) 23*6bd8231aSGregory CLEMENT #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(4) 24*6bd8231aSGregory CLEMENT #define ICPU_GENERAL_CTRL_IF_MASTER_DIS BIT(3) 25*6bd8231aSGregory CLEMENT #define ICPU_GENERAL_CTRL_IF_MASTER_SPI_ENA BIT(2) 26*6bd8231aSGregory CLEMENT #define ICPU_GENERAL_CTRL_IF_MASTER_PI_ENA BIT(1) 27*6bd8231aSGregory CLEMENT 28*6bd8231aSGregory CLEMENT #define ICPU_GENERAL_CTRL_BOOT_MODE_ENA BIT(0) 29*6bd8231aSGregory CLEMENT 30*6bd8231aSGregory CLEMENT #define ICPU_PI_MST_CFG 0x2c 31*6bd8231aSGregory CLEMENT 32*6bd8231aSGregory CLEMENT #define ICPU_PI_MST_CFG_ATE_MODE_DIS BIT(7) 33*6bd8231aSGregory CLEMENT #define ICPU_PI_MST_CFG_CLK_POL BIT(6) 34*6bd8231aSGregory CLEMENT #define ICPU_PI_MST_CFG_TRISTATE_CTRL BIT(5) 35*6bd8231aSGregory CLEMENT #define ICPU_PI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) 36*6bd8231aSGregory CLEMENT #define ICPU_PI_MST_CFG_CLK_DIV_M GENMASK(4, 0) 37*6bd8231aSGregory CLEMENT 38*6bd8231aSGregory CLEMENT #define ICPU_SPI_MST_CFG 0x50 39*6bd8231aSGregory CLEMENT 40*6bd8231aSGregory CLEMENT #define ICPU_SPI_MST_CFG_FAST_READ_ENA BIT(10) 41*6bd8231aSGregory CLEMENT #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME(x) (((x) << 5) & GENMASK(9, 5)) 42*6bd8231aSGregory CLEMENT #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_M GENMASK(9, 5) 43*6bd8231aSGregory CLEMENT #define ICPU_SPI_MST_CFG_CS_DESELECT_TIME_X(x) (((x) & GENMASK(9, 5)) >> 5) 44*6bd8231aSGregory CLEMENT #define ICPU_SPI_MST_CFG_CLK_DIV(x) ((x) & GENMASK(4, 0)) 45*6bd8231aSGregory CLEMENT #define ICPU_SPI_MST_CFG_CLK_DIV_M GENMASK(4, 0) 46*6bd8231aSGregory CLEMENT 47*6bd8231aSGregory CLEMENT #define ICPU_SW_MODE 0x64 48*6bd8231aSGregory CLEMENT 49*6bd8231aSGregory CLEMENT #define ICPU_SW_MODE_SW_PIN_CTRL_MODE BIT(13) 50*6bd8231aSGregory CLEMENT #define ICPU_SW_MODE_SW_SPI_SCK BIT(12) 51*6bd8231aSGregory CLEMENT #define ICPU_SW_MODE_SW_SPI_SCK_OE BIT(11) 52*6bd8231aSGregory CLEMENT #define ICPU_SW_MODE_SW_SPI_SDO BIT(10) 53*6bd8231aSGregory CLEMENT #define ICPU_SW_MODE_SW_SPI_SDO_OE BIT(9) 54*6bd8231aSGregory CLEMENT #define ICPU_SW_MODE_SW_SPI_CS(x) (((x) << 5) & GENMASK(8, 5)) 55*6bd8231aSGregory CLEMENT #define ICPU_SW_MODE_SW_SPI_CS_M GENMASK(8, 5) 56*6bd8231aSGregory CLEMENT #define ICPU_SW_MODE_SW_SPI_CS_X(x) (((x) & GENMASK(8, 5)) >> 5) 57*6bd8231aSGregory CLEMENT #define ICPU_SW_MODE_SW_SPI_CS_OE(x) (((x) << 1) & GENMASK(4, 1)) 58*6bd8231aSGregory CLEMENT #define ICPU_SW_MODE_SW_SPI_CS_OE_M GENMASK(4, 1) 59*6bd8231aSGregory CLEMENT #define ICPU_SW_MODE_SW_SPI_CS_OE_X(x) (((x) & GENMASK(4, 1)) >> 1) 60*6bd8231aSGregory CLEMENT #define ICPU_SW_MODE_SW_SPI_SDI BIT(0) 61*6bd8231aSGregory CLEMENT 62*6bd8231aSGregory CLEMENT #define ICPU_INTR_ENA 0x88 63*6bd8231aSGregory CLEMENT 64*6bd8231aSGregory CLEMENT #define ICPU_INTR_IRQ0_ENA 0x98 65*6bd8231aSGregory CLEMENT #define ICPU_INTR_IRQ0_ENA_IRQ0_ENA BIT(0) 66*6bd8231aSGregory CLEMENT 67*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CTRL 0x234 68*6bd8231aSGregory CLEMENT 69*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CTRL_PWR_DOWN BIT(3) 70*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CTRL_MDSET BIT(2) 71*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CTRL_STALL_REF_ENA BIT(1) 72*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CTRL_INITIALIZE BIT(0) 73*6bd8231aSGregory CLEMENT 74*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG 0x238 75*6bd8231aSGregory CLEMENT 76*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG_DDR_512MBYTE_PLUS BIT(16) 77*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG_DDR_ECC_ERR_ENA BIT(15) 78*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG_DDR_ECC_COR_ENA BIT(14) 79*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG_DDR_ECC_ENA BIT(13) 80*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG_DDR_WIDTH BIT(12) 81*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG_DDR_MODE BIT(11) 82*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG_BURST_SIZE BIT(10) 83*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG_BURST_LEN BIT(9) 84*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG_BANK_CNT BIT(8) 85*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(x) (((x) << 4) & GENMASK(7, 4)) 86*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_M GENMASK(7, 4) 87*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG_MSB_ROW_ADDR_X(x) (((x) & GENMASK(7, 4)) >> 4) 88*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR(x) ((x) & GENMASK(3, 0)) 89*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_CFG_MSB_COL_ADDR_M GENMASK(3, 0) 90*6bd8231aSGregory CLEMENT 91*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_STAT 0x23C 92*6bd8231aSGregory CLEMENT 93*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_STAT_RDATA_MASKED BIT(5) 94*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_STAT_RDATA_DUMMY BIT(4) 95*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_STAT_RDATA_ECC_ERR BIT(3) 96*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_STAT_RDATA_ECC_COR BIT(2) 97*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_STAT_PWR_DOWN_ACK BIT(1) 98*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_STAT_INIT_DONE BIT(0) 99*6bd8231aSGregory CLEMENT 100*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_REF_PERIOD 0x240 101*6bd8231aSGregory CLEMENT 102*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(x) (((x) << 16) & GENMASK(19, 16)) 103*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_M GENMASK(19, 16) 104*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF_X(x) (((x) & GENMASK(19, 16)) >> 16) 105*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(x) ((x) & GENMASK(15, 0)) 106*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD_M GENMASK(15, 0) 107*6bd8231aSGregory CLEMENT 108*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0 0x248 109*6bd8231aSGregory CLEMENT 110*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(x) (((x) << 28) & GENMASK(31, 28)) 111*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_M GENMASK(31, 28) 112*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28) 113*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY(x) (((x) << 24) & GENMASK(27, 24)) 114*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_M GENMASK(27, 24) 115*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_WR_CS_CHANGE_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24) 116*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY(x) (((x) << 20) & GENMASK(23, 20)) 117*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_M GENMASK(23, 20) 118*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_RD_CS_CHANGE_DLY_X(x) (((x) & GENMASK(23, 20)) >> 20) 119*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY(x) (((x) << 16) & GENMASK(19, 16)) 120*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_M GENMASK(19, 16) 121*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_RAS_TO_PRECH_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16) 122*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY(x) (((x) << 12) & GENMASK(15, 12)) 123*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_M GENMASK(15, 12) 124*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_WR_TO_PRECH_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) 125*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY(x) (((x) << 8) & GENMASK(11, 8)) 126*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_M GENMASK(11, 8) 127*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_RD_TO_PRECH_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) 128*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY(x) (((x) << 4) & GENMASK(7, 4)) 129*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_M GENMASK(7, 4) 130*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_WR_DATA_XFR_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) 131*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(x) ((x) & GENMASK(3, 0)) 132*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY_M GENMASK(3, 0) 133*6bd8231aSGregory CLEMENT 134*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1 0x24c 135*6bd8231aSGregory CLEMENT 136*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY(x) (((x) << 24) & GENMASK(31, 24)) 137*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_M GENMASK(31, 24) 138*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_SAME_BANK_DLY_X(x) (((x) & GENMASK(31, 24)) >> 24) 139*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY(x) (((x) << 16) & GENMASK(23, 16)) 140*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_M GENMASK(23, 16) 141*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_BANK8_FAW_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16) 142*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY(x) (((x) << 12) & GENMASK(15, 12)) 143*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_M GENMASK(15, 12) 144*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_PRECH_TO_RAS_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) 145*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY(x) (((x) << 8) & GENMASK(11, 8)) 146*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_M GENMASK(11, 8) 147*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_RAS_TO_RAS_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) 148*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY(x) (((x) << 4) & GENMASK(7, 4)) 149*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_M GENMASK(7, 4) 150*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_RAS_TO_CAS_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) 151*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY(x) ((x) & GENMASK(3, 0)) 152*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING1_WR_TO_RD_DLY_M GENMASK(3, 0) 153*6bd8231aSGregory CLEMENT 154*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING2 0x250 155*6bd8231aSGregory CLEMENT 156*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY(x) (((x) << 28) & GENMASK(31, 28)) 157*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_M GENMASK(31, 28) 158*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING2_PRECH_ALL_DLY_X(x) (((x) & GENMASK(31, 28)) >> 28) 159*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING2_MDSET_DLY(x) (((x) << 24) & GENMASK(27, 24)) 160*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING2_MDSET_DLY_M GENMASK(27, 24) 161*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING2_MDSET_DLY_X(x) (((x) & GENMASK(27, 24)) >> 24) 162*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING2_REF_DLY(x) (((x) << 16) & GENMASK(23, 16)) 163*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING2_REF_DLY_M GENMASK(23, 16) 164*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING2_REF_DLY_X(x) (((x) & GENMASK(23, 16)) >> 16) 165*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY(x) ((x) & GENMASK(15, 0)) 166*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING2_FOUR_HUNDRED_NS_DLY_M GENMASK(15, 0) 167*6bd8231aSGregory CLEMENT 168*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3 0x254 169*6bd8231aSGregory CLEMENT 170*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3_RMW_DLY(x) (((x) << 16) & GENMASK(19, 16)) 171*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3_RMW_DLY_M GENMASK(19, 16) 172*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3_RMW_DLY_X(x) (((x) & GENMASK(19, 16)) >> 16) 173*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY(x) (((x) << 12) & GENMASK(15, 12)) 174*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_M GENMASK(15, 12) 175*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3_ODT_RD_DLY_X(x) (((x) & GENMASK(15, 12)) >> 12) 176*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY(x) (((x) << 8) & GENMASK(11, 8)) 177*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_M GENMASK(11, 8) 178*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3_ODT_WR_DLY_X(x) (((x) & GENMASK(11, 8)) >> 8) 179*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(x) (((x) << 4) & GENMASK(7, 4)) 180*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_M GENMASK(7, 4) 181*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY_X(x) (((x) & GENMASK(7, 4)) >> 4) 182*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY(x) ((x) & GENMASK(3, 0)) 183*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TIMING3_WR_TO_RD_CS_CHANGE_DLY_M GENMASK(3, 0) 184*6bd8231aSGregory CLEMENT 185*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_MR0_VAL 0x258 186*6bd8231aSGregory CLEMENT 187*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_MR1_VAL 0x25c 188*6bd8231aSGregory CLEMENT 189*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_MR2_VAL 0x260 190*6bd8231aSGregory CLEMENT 191*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_MR3_VAL 0x264 192*6bd8231aSGregory CLEMENT 193*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TERMRES_CTRL 0x268 194*6bd8231aSGregory CLEMENT 195*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_EXT BIT(11) 196*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA(x) (((x) << 7) & GENMASK(10, 7)) 197*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_M GENMASK(10, 7) 198*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_RD_ENA_X(x) (((x) & GENMASK(10, 7)) >> 7) 199*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_EXT BIT(6) 200*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA(x) (((x) << 2) & GENMASK(5, 2)) 201*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_M GENMASK(5, 2) 202*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TERMRES_CTRL_ODT_WR_ENA_X(x) (((x) & GENMASK(5, 2)) >> 2) 203*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_EXT BIT(1) 204*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_TERMRES_CTRL_LOCAL_ODT_RD_ENA BIT(0) 205*6bd8231aSGregory CLEMENT 206*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_DQS_DLY(x) (0x270) 207*6bd8231aSGregory CLEMENT 208*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_DQS_DLY_TRAIN_DQ_ENA BIT(11) 209*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1(x) (((x) << 8) & GENMASK(10, 8)) 210*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_M GENMASK(10, 8) 211*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM1_X(x) (((x) & GENMASK(10, 8)) >> 8) 212*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0(x) (((x) << 5) & GENMASK(7, 5)) 213*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_M GENMASK(7, 5) 214*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_TRM0_X(x) (((x) & GENMASK(7, 5)) >> 5) 215*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY(x) ((x) & GENMASK(4, 0)) 216*6bd8231aSGregory CLEMENT #define ICPU_MEMCTRL_DQS_DLY_DQS_DLY_M GENMASK(4, 0) 217*6bd8231aSGregory CLEMENT 218*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_CFG 0x278 219*6bd8231aSGregory CLEMENT 220*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_CFG_PHY_FLUSH_DIS BIT(10) 221*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_CFG_PHY_RD_ADJ_DIS BIT(9) 222*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_CFG_PHY_DQS_EXT BIT(8) 223*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_CFG_PHY_FIFO_RST BIT(7) 224*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_CFG_PHY_DLL_BL_RST BIT(6) 225*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_CFG_PHY_DLL_CL_RST BIT(5) 226*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_CFG_PHY_ODT_OE BIT(4) 227*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_CFG_PHY_CK_OE BIT(3) 228*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_CFG_PHY_CL_OE BIT(2) 229*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_CFG_PHY_SSTL_ENA BIT(1) 230*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_CFG_PHY_RST BIT(0) 231*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_DQ_DLY_TRM 0x180 232*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_DQ_DLY_TRM_RSZ 0x4 233*6bd8231aSGregory CLEMENT 234*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_ZCAL 0x294 235*6bd8231aSGregory CLEMENT 236*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_ZCAL_ZCAL_CLK_SEL BIT(9) 237*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT(x) (((x) << 5) & GENMASK(8, 5)) 238*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_M GENMASK(8, 5) 239*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_ODT_X(x) (((x) & GENMASK(8, 5)) >> 5) 240*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_ZCAL_ZCAL_PROG(x) (((x) << 1) & GENMASK(4, 1)) 241*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_M GENMASK(4, 1) 242*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_ZCAL_ZCAL_PROG_X(x) (((x) & GENMASK(4, 1)) >> 1) 243*6bd8231aSGregory CLEMENT #define ICPU_MEMPHY_ZCAL_ZCAL_ENA BIT(0) 244*6bd8231aSGregory CLEMENT 245*6bd8231aSGregory CLEMENT #endif 246