1e66f840cSTristram Ha /* SPDX-License-Identifier: GPL-2.0-or-later */ 2e66f840cSTristram Ha /* 3e66f840cSTristram Ha * Microchip KSZ8795 register definitions 4e66f840cSTristram Ha * 5e66f840cSTristram Ha * Copyright (c) 2017 Microchip Technology Inc. 6e66f840cSTristram Ha * Tristram Ha <Tristram.Ha@microchip.com> 7e66f840cSTristram Ha */ 8e66f840cSTristram Ha 9e66f840cSTristram Ha #ifndef __KSZ8795_REG_H 10e66f840cSTristram Ha #define __KSZ8795_REG_H 11e66f840cSTristram Ha 12e66f840cSTristram Ha #define KS_PORT_M 0x1F 13e66f840cSTristram Ha 14e66f840cSTristram Ha #define KS_PRIO_M 0x3 15e66f840cSTristram Ha #define KS_PRIO_S 2 16e66f840cSTristram Ha 17e66f840cSTristram Ha #define SW_REVISION_M 0x0E 18e66f840cSTristram Ha #define SW_REVISION_S 1 19e66f840cSTristram Ha 204b20a07eSOleksij Rempel #define KSZ8863_REG_SW_RESET 0x43 214b20a07eSOleksij Rempel 224b20a07eSOleksij Rempel #define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4) 234b20a07eSOleksij Rempel #define KSZ8863_PCS_RESET BIT(0) 24e66f840cSTristram Ha 25e66f840cSTristram Ha #define REG_SW_CTRL_0 0x02 26e66f840cSTristram Ha 27e66f840cSTristram Ha #define SW_NEW_BACKOFF BIT(7) 28e66f840cSTristram Ha #define SW_GLOBAL_RESET BIT(6) 29e66f840cSTristram Ha #define SW_FLUSH_DYN_MAC_TABLE BIT(5) 30e66f840cSTristram Ha #define SW_FLUSH_STA_MAC_TABLE BIT(4) 31e66f840cSTristram Ha #define SW_LINK_AUTO_AGING BIT(0) 32e66f840cSTristram Ha 33e66f840cSTristram Ha #define REG_SW_CTRL_1 0x03 34e66f840cSTristram Ha 35e66f840cSTristram Ha #define SW_HUGE_PACKET BIT(6) 36e66f840cSTristram Ha #define SW_TX_FLOW_CTRL_DISABLE BIT(5) 37e66f840cSTristram Ha #define SW_RX_FLOW_CTRL_DISABLE BIT(4) 38e66f840cSTristram Ha #define SW_CHECK_LENGTH BIT(3) 39e66f840cSTristram Ha #define SW_AGING_ENABLE BIT(2) 40e66f840cSTristram Ha #define SW_FAST_AGING BIT(1) 41e66f840cSTristram Ha #define SW_AGGR_BACKOFF BIT(0) 42e66f840cSTristram Ha 43e66f840cSTristram Ha #define REG_SW_CTRL_2 0x04 44e66f840cSTristram Ha 45e66f840cSTristram Ha #define UNICAST_VLAN_BOUNDARY BIT(7) 46e66f840cSTristram Ha #define SW_BACK_PRESSURE BIT(5) 47e66f840cSTristram Ha #define FAIR_FLOW_CTRL BIT(4) 48e66f840cSTristram Ha #define NO_EXC_COLLISION_DROP BIT(3) 49e66f840cSTristram Ha #define SW_LEGAL_PACKET_DISABLE BIT(1) 50e66f840cSTristram Ha 51*29d1e85fSOleksij Rempel #define KSZ8863_HUGE_PACKET_ENABLE BIT(2) 52*29d1e85fSOleksij Rempel #define KSZ8863_LEGAL_PACKET_ENABLE BIT(1) 53*29d1e85fSOleksij Rempel 54e66f840cSTristram Ha #define REG_SW_CTRL_3 0x05 55e66f840cSTristram Ha #define WEIGHTED_FAIR_QUEUE_ENABLE BIT(3) 56e66f840cSTristram Ha 57e66f840cSTristram Ha #define SW_VLAN_ENABLE BIT(7) 58e66f840cSTristram Ha #define SW_IGMP_SNOOP BIT(6) 59e66f840cSTristram Ha #define SW_MIRROR_RX_TX BIT(0) 60e66f840cSTristram Ha 61e66f840cSTristram Ha #define REG_SW_CTRL_4 0x06 62e66f840cSTristram Ha 63e66f840cSTristram Ha #define SW_HALF_DUPLEX_FLOW_CTRL BIT(7) 64e66f840cSTristram Ha #define SW_HALF_DUPLEX BIT(6) 65e66f840cSTristram Ha #define SW_FLOW_CTRL BIT(5) 66e66f840cSTristram Ha #define SW_10_MBIT BIT(4) 67e66f840cSTristram Ha #define SW_REPLACE_VID BIT(3) 68e66f840cSTristram Ha 69e66f840cSTristram Ha #define REG_SW_CTRL_5 0x07 70e66f840cSTristram Ha 71e66f840cSTristram Ha #define REG_SW_CTRL_6 0x08 72e66f840cSTristram Ha 73e66f840cSTristram Ha #define SW_MIB_COUNTER_FLUSH BIT(7) 74e66f840cSTristram Ha #define SW_MIB_COUNTER_FREEZE BIT(6) 75e66f840cSTristram Ha #define SW_MIB_COUNTER_CTRL_ENABLE KS_PORT_M 76e66f840cSTristram Ha 77e66f840cSTristram Ha #define REG_SW_CTRL_9 0x0B 78e66f840cSTristram Ha 79e66f840cSTristram Ha #define SPI_CLK_125_MHZ 0x80 80e66f840cSTristram Ha #define SPI_CLK_62_5_MHZ 0x40 81e66f840cSTristram Ha #define SPI_CLK_31_25_MHZ 0x00 82e66f840cSTristram Ha 83e66f840cSTristram Ha #define SW_LED_MODE_M 0x3 84e66f840cSTristram Ha #define SW_LED_MODE_S 4 85e66f840cSTristram Ha #define SW_LED_LINK_ACT_SPEED 0 86e66f840cSTristram Ha #define SW_LED_LINK_ACT 1 87e66f840cSTristram Ha #define SW_LED_LINK_ACT_DUPLEX 2 88e66f840cSTristram Ha #define SW_LED_LINK_DUPLEX 3 89e66f840cSTristram Ha 90e66f840cSTristram Ha #define REG_SW_CTRL_10 0x0C 91e66f840cSTristram Ha 92e66f840cSTristram Ha #define SW_PASS_PAUSE BIT(0) 93e66f840cSTristram Ha 94e66f840cSTristram Ha #define REG_SW_CTRL_11 0x0D 95e66f840cSTristram Ha 96e66f840cSTristram Ha #define REG_POWER_MANAGEMENT_1 0x0E 97e66f840cSTristram Ha 98e66f840cSTristram Ha #define SW_PLL_POWER_DOWN BIT(5) 99e66f840cSTristram Ha #define SW_POWER_MANAGEMENT_MODE_M 0x3 100e66f840cSTristram Ha #define SW_POWER_MANAGEMENT_MODE_S 3 101e66f840cSTristram Ha #define SW_POWER_NORMAL 0 102e66f840cSTristram Ha #define SW_ENERGY_DETECTION 1 103e66f840cSTristram Ha #define SW_SOFTWARE_POWER_DOWN 2 104e66f840cSTristram Ha 105e66f840cSTristram Ha #define REG_POWER_MANAGEMENT_2 0x0F 106e66f840cSTristram Ha 107e66f840cSTristram Ha #define REG_PORT_1_CTRL_0 0x10 108e66f840cSTristram Ha #define REG_PORT_2_CTRL_0 0x20 109e66f840cSTristram Ha #define REG_PORT_3_CTRL_0 0x30 110e66f840cSTristram Ha #define REG_PORT_4_CTRL_0 0x40 111e66f840cSTristram Ha #define REG_PORT_5_CTRL_0 0x50 112e66f840cSTristram Ha 113e66f840cSTristram Ha #define PORT_BROADCAST_STORM BIT(7) 114e66f840cSTristram Ha #define PORT_DIFFSERV_ENABLE BIT(6) 115e66f840cSTristram Ha #define PORT_802_1P_ENABLE BIT(5) 116e66f840cSTristram Ha #define PORT_BASED_PRIO_S 3 117e66f840cSTristram Ha #define PORT_BASED_PRIO_M KS_PRIO_M 118e66f840cSTristram Ha #define PORT_BASED_PRIO_0 0 119e66f840cSTristram Ha #define PORT_BASED_PRIO_1 1 120e66f840cSTristram Ha #define PORT_BASED_PRIO_2 2 121e66f840cSTristram Ha #define PORT_BASED_PRIO_3 3 122e66f840cSTristram Ha #define PORT_INSERT_TAG BIT(2) 123e66f840cSTristram Ha #define PORT_REMOVE_TAG BIT(1) 124e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_L BIT(0) 125e66f840cSTristram Ha 126e66f840cSTristram Ha #define REG_PORT_1_CTRL_1 0x11 127e66f840cSTristram Ha #define REG_PORT_2_CTRL_1 0x21 128e66f840cSTristram Ha #define REG_PORT_3_CTRL_1 0x31 129e66f840cSTristram Ha #define REG_PORT_4_CTRL_1 0x41 130e66f840cSTristram Ha #define REG_PORT_5_CTRL_1 0x51 131e66f840cSTristram Ha 132e66f840cSTristram Ha #define PORT_MIRROR_SNIFFER BIT(7) 133e66f840cSTristram Ha #define PORT_MIRROR_RX BIT(6) 134e66f840cSTristram Ha #define PORT_MIRROR_TX BIT(5) 135e66f840cSTristram Ha #define PORT_VLAN_MEMBERSHIP KS_PORT_M 136e66f840cSTristram Ha 137e66f840cSTristram Ha #define REG_PORT_1_CTRL_2 0x12 138e66f840cSTristram Ha #define REG_PORT_2_CTRL_2 0x22 139e66f840cSTristram Ha #define REG_PORT_3_CTRL_2 0x32 140e66f840cSTristram Ha #define REG_PORT_4_CTRL_2 0x42 141e66f840cSTristram Ha #define REG_PORT_5_CTRL_2 0x52 142e66f840cSTristram Ha 143e66f840cSTristram Ha #define PORT_INGRESS_FILTER BIT(6) 144e66f840cSTristram Ha #define PORT_DISCARD_NON_VID BIT(5) 145e66f840cSTristram Ha #define PORT_FORCE_FLOW_CTRL BIT(4) 146e66f840cSTristram Ha #define PORT_BACK_PRESSURE BIT(3) 147e66f840cSTristram Ha 148e66f840cSTristram Ha #define REG_PORT_1_CTRL_3 0x13 149e66f840cSTristram Ha #define REG_PORT_2_CTRL_3 0x23 150e66f840cSTristram Ha #define REG_PORT_3_CTRL_3 0x33 151e66f840cSTristram Ha #define REG_PORT_4_CTRL_3 0x43 152e66f840cSTristram Ha #define REG_PORT_5_CTRL_3 0x53 153e66f840cSTristram Ha #define REG_PORT_1_CTRL_4 0x14 154e66f840cSTristram Ha #define REG_PORT_2_CTRL_4 0x24 155e66f840cSTristram Ha #define REG_PORT_3_CTRL_4 0x34 156e66f840cSTristram Ha #define REG_PORT_4_CTRL_4 0x44 157e66f840cSTristram Ha #define REG_PORT_5_CTRL_4 0x54 158e66f840cSTristram Ha 159e66f840cSTristram Ha #define PORT_DEFAULT_VID 0x0001 160e66f840cSTristram Ha 161e66f840cSTristram Ha #define REG_PORT_1_CTRL_5 0x15 162e66f840cSTristram Ha #define REG_PORT_2_CTRL_5 0x25 163e66f840cSTristram Ha #define REG_PORT_3_CTRL_5 0x35 164e66f840cSTristram Ha #define REG_PORT_4_CTRL_5 0x45 165e66f840cSTristram Ha #define REG_PORT_5_CTRL_5 0x55 166e66f840cSTristram Ha 167e66f840cSTristram Ha #define PORT_ACL_ENABLE BIT(2) 168e66f840cSTristram Ha #define PORT_AUTHEN_MODE 0x3 169e66f840cSTristram Ha #define PORT_AUTHEN_PASS 0 170e66f840cSTristram Ha #define PORT_AUTHEN_BLOCK 1 171e66f840cSTristram Ha #define PORT_AUTHEN_TRAP 2 172e66f840cSTristram Ha 173e66f840cSTristram Ha #define REG_PORT_5_CTRL_6 0x56 174e66f840cSTristram Ha 175e66f840cSTristram Ha #define PORT_MII_INTERNAL_CLOCK BIT(7) 176e66f840cSTristram Ha #define PORT_GMII_MAC_MODE BIT(2) 177e66f840cSTristram Ha 178e66f840cSTristram Ha #define REG_PORT_1_CTRL_7 0x17 179e66f840cSTristram Ha #define REG_PORT_2_CTRL_7 0x27 180e66f840cSTristram Ha #define REG_PORT_3_CTRL_7 0x37 181e66f840cSTristram Ha #define REG_PORT_4_CTRL_7 0x47 182e66f840cSTristram Ha 183e66f840cSTristram Ha #define PORT_AUTO_NEG_ASYM_PAUSE BIT(5) 184e66f840cSTristram Ha #define PORT_AUTO_NEG_SYM_PAUSE BIT(4) 185e66f840cSTristram Ha #define PORT_AUTO_NEG_100BTX_FD BIT(3) 186e66f840cSTristram Ha #define PORT_AUTO_NEG_100BTX BIT(2) 187e66f840cSTristram Ha #define PORT_AUTO_NEG_10BT_FD BIT(1) 188e66f840cSTristram Ha #define PORT_AUTO_NEG_10BT BIT(0) 189e66f840cSTristram Ha 190e66f840cSTristram Ha #define REG_PORT_1_STATUS_0 0x18 191e66f840cSTristram Ha #define REG_PORT_2_STATUS_0 0x28 192e66f840cSTristram Ha #define REG_PORT_3_STATUS_0 0x38 193e66f840cSTristram Ha #define REG_PORT_4_STATUS_0 0x48 194e66f840cSTristram Ha 195e66f840cSTristram Ha /* For KSZ8765. */ 196e66f840cSTristram Ha #define PORT_REMOTE_ASYM_PAUSE BIT(5) 197e66f840cSTristram Ha #define PORT_REMOTE_SYM_PAUSE BIT(4) 198e66f840cSTristram Ha #define PORT_REMOTE_100BTX_FD BIT(3) 199e66f840cSTristram Ha #define PORT_REMOTE_100BTX BIT(2) 200e66f840cSTristram Ha #define PORT_REMOTE_10BT_FD BIT(1) 201e66f840cSTristram Ha #define PORT_REMOTE_10BT BIT(0) 202e66f840cSTristram Ha 203e66f840cSTristram Ha #define REG_PORT_1_STATUS_1 0x19 204e66f840cSTristram Ha #define REG_PORT_2_STATUS_1 0x29 205e66f840cSTristram Ha #define REG_PORT_3_STATUS_1 0x39 206e66f840cSTristram Ha #define REG_PORT_4_STATUS_1 0x49 207e66f840cSTristram Ha 208e66f840cSTristram Ha #define PORT_HP_MDIX BIT(7) 209e66f840cSTristram Ha #define PORT_REVERSED_POLARITY BIT(5) 210e66f840cSTristram Ha #define PORT_TX_FLOW_CTRL BIT(4) 211e66f840cSTristram Ha #define PORT_RX_FLOW_CTRL BIT(3) 212e66f840cSTristram Ha #define PORT_STAT_SPEED_100MBIT BIT(2) 213e66f840cSTristram Ha #define PORT_STAT_FULL_DUPLEX BIT(1) 214e66f840cSTristram Ha 215e66f840cSTristram Ha #define PORT_REMOTE_FAULT BIT(0) 216e66f840cSTristram Ha 217e66f840cSTristram Ha #define REG_PORT_1_LINK_MD_CTRL 0x1A 218e66f840cSTristram Ha #define REG_PORT_2_LINK_MD_CTRL 0x2A 219e66f840cSTristram Ha #define REG_PORT_3_LINK_MD_CTRL 0x3A 220e66f840cSTristram Ha #define REG_PORT_4_LINK_MD_CTRL 0x4A 221e66f840cSTristram Ha 222e66f840cSTristram Ha #define PORT_CABLE_10M_SHORT BIT(7) 22336838050SOleksij Rempel #define PORT_CABLE_DIAG_RESULT_M GENMASK(6, 5) 224e66f840cSTristram Ha #define PORT_CABLE_DIAG_RESULT_S 5 225e66f840cSTristram Ha #define PORT_CABLE_STAT_NORMAL 0 226e66f840cSTristram Ha #define PORT_CABLE_STAT_OPEN 1 227e66f840cSTristram Ha #define PORT_CABLE_STAT_SHORT 2 228e66f840cSTristram Ha #define PORT_CABLE_STAT_FAILED 3 229e66f840cSTristram Ha #define PORT_START_CABLE_DIAG BIT(4) 230e66f840cSTristram Ha #define PORT_FORCE_LINK BIT(3) 231e66f840cSTristram Ha #define PORT_POWER_SAVING BIT(2) 232e66f840cSTristram Ha #define PORT_PHY_REMOTE_LOOPBACK BIT(1) 233e66f840cSTristram Ha #define PORT_CABLE_FAULT_COUNTER_H 0x01 234e66f840cSTristram Ha 235e66f840cSTristram Ha #define REG_PORT_1_LINK_MD_RESULT 0x1B 236e66f840cSTristram Ha #define REG_PORT_2_LINK_MD_RESULT 0x2B 237e66f840cSTristram Ha #define REG_PORT_3_LINK_MD_RESULT 0x3B 238e66f840cSTristram Ha #define REG_PORT_4_LINK_MD_RESULT 0x4B 239e66f840cSTristram Ha 240e66f840cSTristram Ha #define PORT_CABLE_FAULT_COUNTER_L 0xFF 241e66f840cSTristram Ha #define PORT_CABLE_FAULT_COUNTER 0x1FF 242e66f840cSTristram Ha 243e66f840cSTristram Ha #define REG_PORT_1_CTRL_9 0x1C 244e66f840cSTristram Ha #define REG_PORT_2_CTRL_9 0x2C 245e66f840cSTristram Ha #define REG_PORT_3_CTRL_9 0x3C 246e66f840cSTristram Ha #define REG_PORT_4_CTRL_9 0x4C 247e66f840cSTristram Ha 2484b20a07eSOleksij Rempel #define PORT_AUTO_NEG_ENABLE BIT(7) 249e66f840cSTristram Ha #define PORT_AUTO_NEG_DISABLE BIT(7) 250e66f840cSTristram Ha #define PORT_FORCE_100_MBIT BIT(6) 251e66f840cSTristram Ha #define PORT_FORCE_FULL_DUPLEX BIT(5) 252e66f840cSTristram Ha 253e66f840cSTristram Ha #define REG_PORT_1_CTRL_10 0x1D 254e66f840cSTristram Ha #define REG_PORT_2_CTRL_10 0x2D 255e66f840cSTristram Ha #define REG_PORT_3_CTRL_10 0x3D 256e66f840cSTristram Ha #define REG_PORT_4_CTRL_10 0x4D 257e66f840cSTristram Ha 258e66f840cSTristram Ha #define PORT_LED_OFF BIT(7) 259e66f840cSTristram Ha #define PORT_TX_DISABLE BIT(6) 260e66f840cSTristram Ha #define PORT_AUTO_NEG_RESTART BIT(5) 261e66f840cSTristram Ha #define PORT_POWER_DOWN BIT(3) 262e66f840cSTristram Ha #define PORT_AUTO_MDIX_DISABLE BIT(2) 263e66f840cSTristram Ha #define PORT_FORCE_MDIX BIT(1) 264e66f840cSTristram Ha #define PORT_MAC_LOOPBACK BIT(0) 265e66f840cSTristram Ha 266e66f840cSTristram Ha #define REG_PORT_1_STATUS_2 0x1E 267e66f840cSTristram Ha #define REG_PORT_2_STATUS_2 0x2E 268e66f840cSTristram Ha #define REG_PORT_3_STATUS_2 0x3E 269e66f840cSTristram Ha #define REG_PORT_4_STATUS_2 0x4E 270e66f840cSTristram Ha 271e66f840cSTristram Ha #define PORT_MDIX_STATUS BIT(7) 272e66f840cSTristram Ha #define PORT_AUTO_NEG_COMPLETE BIT(6) 273e66f840cSTristram Ha #define PORT_STAT_LINK_GOOD BIT(5) 274e66f840cSTristram Ha 275e66f840cSTristram Ha #define REG_PORT_1_STATUS_3 0x1F 276e66f840cSTristram Ha #define REG_PORT_2_STATUS_3 0x2F 277e66f840cSTristram Ha #define REG_PORT_3_STATUS_3 0x3F 278e66f840cSTristram Ha #define REG_PORT_4_STATUS_3 0x4F 279e66f840cSTristram Ha 280e66f840cSTristram Ha #define PORT_PHY_LOOPBACK BIT(7) 281e66f840cSTristram Ha #define PORT_PHY_ISOLATE BIT(5) 282e66f840cSTristram Ha #define PORT_PHY_SOFT_RESET BIT(4) 283e66f840cSTristram Ha #define PORT_PHY_FORCE_LINK BIT(3) 284e66f840cSTristram Ha #define PORT_PHY_MODE_M 0x7 285e66f840cSTristram Ha #define PHY_MODE_IN_AUTO_NEG 1 286e66f840cSTristram Ha #define PHY_MODE_10BT_HALF 2 287e66f840cSTristram Ha #define PHY_MODE_100BT_HALF 3 288e66f840cSTristram Ha #define PHY_MODE_10BT_FULL 5 289e66f840cSTristram Ha #define PHY_MODE_100BT_FULL 6 290e66f840cSTristram Ha #define PHY_MODE_ISOLDATE 7 291e66f840cSTristram Ha 292e66f840cSTristram Ha #define REG_PORT_CTRL_0 0x00 293e66f840cSTristram Ha #define REG_PORT_CTRL_1 0x01 294e66f840cSTristram Ha #define REG_PORT_CTRL_2 0x02 295e66f840cSTristram Ha #define REG_PORT_CTRL_VID 0x03 296e66f840cSTristram Ha 297e66f840cSTristram Ha #define REG_PORT_CTRL_5 0x05 298e66f840cSTristram Ha 299e66f840cSTristram Ha #define REG_PORT_STATUS_1 0x09 300e66f840cSTristram Ha #define REG_PORT_LINK_MD_CTRL 0x0A 301e66f840cSTristram Ha #define REG_PORT_LINK_MD_RESULT 0x0B 302e66f840cSTristram Ha #define REG_PORT_CTRL_9 0x0C 303e66f840cSTristram Ha #define REG_PORT_CTRL_10 0x0D 304e66f840cSTristram Ha #define REG_PORT_STATUS_3 0x0F 305e66f840cSTristram Ha 306e66f840cSTristram Ha #define REG_PORT_CTRL_12 0xA0 307e66f840cSTristram Ha #define REG_PORT_CTRL_13 0xA1 308e66f840cSTristram Ha #define REG_PORT_RATE_CTRL_3 0xA2 309e66f840cSTristram Ha #define REG_PORT_RATE_CTRL_2 0xA3 310e66f840cSTristram Ha #define REG_PORT_RATE_CTRL_1 0xA4 311e66f840cSTristram Ha #define REG_PORT_RATE_CTRL_0 0xA5 312e66f840cSTristram Ha #define REG_PORT_RATE_LIMIT 0xA6 313e66f840cSTristram Ha #define REG_PORT_IN_RATE_0 0xA7 314e66f840cSTristram Ha #define REG_PORT_IN_RATE_1 0xA8 315e66f840cSTristram Ha #define REG_PORT_IN_RATE_2 0xA9 316e66f840cSTristram Ha #define REG_PORT_IN_RATE_3 0xAA 317e66f840cSTristram Ha #define REG_PORT_OUT_RATE_0 0xAB 318e66f840cSTristram Ha #define REG_PORT_OUT_RATE_1 0xAC 319e66f840cSTristram Ha #define REG_PORT_OUT_RATE_2 0xAD 320e66f840cSTristram Ha #define REG_PORT_OUT_RATE_3 0xAE 321e66f840cSTristram Ha 322e66f840cSTristram Ha #define PORT_CTRL_ADDR(port, addr) \ 323e66f840cSTristram Ha ((addr) + REG_PORT_1_CTRL_0 + (port) * \ 324e66f840cSTristram Ha (REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0)) 325e66f840cSTristram Ha 326e66f840cSTristram Ha #define REG_SW_MAC_ADDR_0 0x68 327e66f840cSTristram Ha #define REG_SW_MAC_ADDR_1 0x69 328e66f840cSTristram Ha #define REG_SW_MAC_ADDR_2 0x6A 329e66f840cSTristram Ha #define REG_SW_MAC_ADDR_3 0x6B 330e66f840cSTristram Ha #define REG_SW_MAC_ADDR_4 0x6C 331e66f840cSTristram Ha #define REG_SW_MAC_ADDR_5 0x6D 332e66f840cSTristram Ha 333e66f840cSTristram Ha #define TABLE_EXT_SELECT_S 5 334e66f840cSTristram Ha #define TABLE_EEE_V 1 335e66f840cSTristram Ha #define TABLE_ACL_V 2 336e66f840cSTristram Ha #define TABLE_PME_V 4 337e66f840cSTristram Ha #define TABLE_LINK_MD_V 5 338e66f840cSTristram Ha #define TABLE_EEE (TABLE_EEE_V << TABLE_EXT_SELECT_S) 339e66f840cSTristram Ha #define TABLE_ACL (TABLE_ACL_V << TABLE_EXT_SELECT_S) 340e66f840cSTristram Ha #define TABLE_PME (TABLE_PME_V << TABLE_EXT_SELECT_S) 341e66f840cSTristram Ha #define TABLE_LINK_MD (TABLE_LINK_MD << TABLE_EXT_SELECT_S) 342e66f840cSTristram Ha #define TABLE_READ BIT(4) 343e66f840cSTristram Ha #define TABLE_SELECT_S 2 344e66f840cSTristram Ha #define TABLE_STATIC_MAC_V 0 345e66f840cSTristram Ha #define TABLE_VLAN_V 1 346e66f840cSTristram Ha #define TABLE_DYNAMIC_MAC_V 2 347e66f840cSTristram Ha #define TABLE_MIB_V 3 348e66f840cSTristram Ha #define TABLE_STATIC_MAC (TABLE_STATIC_MAC_V << TABLE_SELECT_S) 349e66f840cSTristram Ha #define TABLE_VLAN (TABLE_VLAN_V << TABLE_SELECT_S) 350e66f840cSTristram Ha #define TABLE_DYNAMIC_MAC (TABLE_DYNAMIC_MAC_V << TABLE_SELECT_S) 351e66f840cSTristram Ha #define TABLE_MIB (TABLE_MIB_V << TABLE_SELECT_S) 352e66f840cSTristram Ha 353e66f840cSTristram Ha #define REG_IND_CTRL_1 0x6F 354e66f840cSTristram Ha 355e66f840cSTristram Ha #define TABLE_ENTRY_MASK 0x03FF 356e66f840cSTristram Ha #define TABLE_EXT_ENTRY_MASK 0x0FFF 357e66f840cSTristram Ha 358e66f840cSTristram Ha #define REG_IND_DATA_5 0x73 359e66f840cSTristram Ha #define REG_IND_DATA_2 0x76 360e66f840cSTristram Ha #define REG_IND_DATA_1 0x77 361e66f840cSTristram Ha #define REG_IND_DATA_0 0x78 362e66f840cSTristram Ha 363e66f840cSTristram Ha #define REG_IND_DATA_PME_EEE_ACL 0xA0 364e66f840cSTristram Ha 365e66f840cSTristram Ha #define REG_INT_STATUS 0x7C 366e66f840cSTristram Ha #define REG_INT_ENABLE 0x7D 367e66f840cSTristram Ha 368e66f840cSTristram Ha #define INT_PME BIT(4) 369e66f840cSTristram Ha 370e66f840cSTristram Ha #define REG_ACL_INT_STATUS 0x7E 371e66f840cSTristram Ha #define REG_ACL_INT_ENABLE 0x7F 372e66f840cSTristram Ha 373e66f840cSTristram Ha #define INT_PORT_5 BIT(4) 374e66f840cSTristram Ha #define INT_PORT_4 BIT(3) 375e66f840cSTristram Ha #define INT_PORT_3 BIT(2) 376e66f840cSTristram Ha #define INT_PORT_2 BIT(1) 377e66f840cSTristram Ha #define INT_PORT_1 BIT(0) 378e66f840cSTristram Ha 379e66f840cSTristram Ha #define INT_PORT_ALL \ 380e66f840cSTristram Ha (INT_PORT_5 | INT_PORT_4 | INT_PORT_3 | INT_PORT_2 | INT_PORT_1) 381e66f840cSTristram Ha 382e66f840cSTristram Ha #define REG_SW_CTRL_12 0x80 383e66f840cSTristram Ha #define REG_SW_CTRL_13 0x81 384e66f840cSTristram Ha 385e66f840cSTristram Ha #define SWITCH_802_1P_MASK 3 386e66f840cSTristram Ha #define SWITCH_802_1P_BASE 3 387e66f840cSTristram Ha #define SWITCH_802_1P_SHIFT 2 388e66f840cSTristram Ha 389e66f840cSTristram Ha #define SW_802_1P_MAP_M KS_PRIO_M 390e66f840cSTristram Ha #define SW_802_1P_MAP_S KS_PRIO_S 391e66f840cSTristram Ha 392e66f840cSTristram Ha #define REG_SWITCH_CTRL_14 0x82 393e66f840cSTristram Ha 394e66f840cSTristram Ha #define SW_PRIO_MAPPING_M KS_PRIO_M 395e66f840cSTristram Ha #define SW_PRIO_MAPPING_S 6 396e66f840cSTristram Ha #define SW_PRIO_MAP_3_HI 0 397e66f840cSTristram Ha #define SW_PRIO_MAP_2_HI 2 398e66f840cSTristram Ha #define SW_PRIO_MAP_0_LO 3 399e66f840cSTristram Ha 400e66f840cSTristram Ha #define REG_SW_CTRL_15 0x83 401e66f840cSTristram Ha #define REG_SW_CTRL_16 0x84 402e66f840cSTristram Ha #define REG_SW_CTRL_17 0x85 403e66f840cSTristram Ha #define REG_SW_CTRL_18 0x86 404e66f840cSTristram Ha 405e66f840cSTristram Ha #define SW_SELF_ADDR_FILTER_ENABLE BIT(6) 406e66f840cSTristram Ha 407e66f840cSTristram Ha #define REG_SW_UNK_UCAST_CTRL 0x83 408e66f840cSTristram Ha #define REG_SW_UNK_MCAST_CTRL 0x84 409e66f840cSTristram Ha #define REG_SW_UNK_VID_CTRL 0x85 410e66f840cSTristram Ha #define REG_SW_UNK_IP_MCAST_CTRL 0x86 411e66f840cSTristram Ha 412e66f840cSTristram Ha #define SW_UNK_FWD_ENABLE BIT(5) 413e66f840cSTristram Ha #define SW_UNK_FWD_MAP KS_PORT_M 414e66f840cSTristram Ha 415e66f840cSTristram Ha #define REG_SW_CTRL_19 0x87 416e66f840cSTristram Ha 417e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_PERIOD_M 0x3 418e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_PERIOD_S 4 419e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_16_MS 0 420e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_64_MS 1 421e66f840cSTristram Ha #define SW_IN_RATE_LIMIT_256_MS 2 422e66f840cSTristram Ha #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3) 423e66f840cSTristram Ha #define SW_INS_TAG_ENABLE BIT(2) 424e66f840cSTristram Ha 425e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_0 0x90 426e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_1 0x91 427e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_2 0x92 428e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_3 0x93 429e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_4 0x94 430e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_5 0x95 431e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_6 0x96 432e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_7 0x97 433e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_8 0x98 434e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_9 0x99 435e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_10 0x9A 436e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_11 0x9B 437e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_12 0x9C 438e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_13 0x9D 439e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_14 0x9E 440e66f840cSTristram Ha #define REG_TOS_PRIO_CTRL_15 0x9F 441e66f840cSTristram Ha 442e66f840cSTristram Ha #define TOS_PRIO_M KS_PRIO_M 443e66f840cSTristram Ha #define TOS_PRIO_S KS_PRIO_S 444e66f840cSTristram Ha 445e66f840cSTristram Ha #define REG_SW_CTRL_20 0xA3 446e66f840cSTristram Ha 447e66f840cSTristram Ha #define SW_GMII_DRIVE_STRENGTH_S 4 448e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_M 0x7 449e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_2MA 0 450e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_4MA 1 451e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_8MA 2 452e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_12MA 3 453e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_16MA 4 454e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_20MA 5 455e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_24MA 6 456e66f840cSTristram Ha #define SW_DRIVE_STRENGTH_28MA 7 457e66f840cSTristram Ha #define SW_MII_DRIVE_STRENGTH_S 0 458e66f840cSTristram Ha 459e66f840cSTristram Ha #define REG_SW_CTRL_21 0xA4 460e66f840cSTristram Ha 461e66f840cSTristram Ha #define SW_IPV6_MLD_OPTION BIT(3) 462e66f840cSTristram Ha #define SW_IPV6_MLD_SNOOP BIT(2) 463e66f840cSTristram Ha 464e66f840cSTristram Ha #define REG_PORT_1_CTRL_12 0xB0 465e66f840cSTristram Ha #define REG_PORT_2_CTRL_12 0xC0 466e66f840cSTristram Ha #define REG_PORT_3_CTRL_12 0xD0 467e66f840cSTristram Ha #define REG_PORT_4_CTRL_12 0xE0 468e66f840cSTristram Ha #define REG_PORT_5_CTRL_12 0xF0 469e66f840cSTristram Ha 470e66f840cSTristram Ha #define PORT_PASS_ALL BIT(6) 471e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_5_S 3 472e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_5 BIT(3) 473e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_4 BIT(2) 474e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_3 BIT(1) 475e66f840cSTristram Ha #define PORT_INS_TAG_FOR_PORT_2 BIT(0) 476e66f840cSTristram Ha 477e66f840cSTristram Ha #define REG_PORT_1_CTRL_13 0xB1 478e66f840cSTristram Ha #define REG_PORT_2_CTRL_13 0xC1 479e66f840cSTristram Ha #define REG_PORT_3_CTRL_13 0xD1 480e66f840cSTristram Ha #define REG_PORT_4_CTRL_13 0xE1 481e66f840cSTristram Ha #define REG_PORT_5_CTRL_13 0xF1 482e66f840cSTristram Ha 483e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_H BIT(1) 484e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_1 0 485e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_2 1 486e66f840cSTristram Ha #define PORT_QUEUE_SPLIT_4 2 487e66f840cSTristram Ha #define PORT_DROP_TAG BIT(0) 488e66f840cSTristram Ha 489e66f840cSTristram Ha #define REG_PORT_1_CTRL_14 0xB2 490e66f840cSTristram Ha #define REG_PORT_2_CTRL_14 0xC2 491e66f840cSTristram Ha #define REG_PORT_3_CTRL_14 0xD2 492e66f840cSTristram Ha #define REG_PORT_4_CTRL_14 0xE2 493e66f840cSTristram Ha #define REG_PORT_5_CTRL_14 0xF2 494e66f840cSTristram Ha #define REG_PORT_1_CTRL_15 0xB3 495e66f840cSTristram Ha #define REG_PORT_2_CTRL_15 0xC3 496e66f840cSTristram Ha #define REG_PORT_3_CTRL_15 0xD3 497e66f840cSTristram Ha #define REG_PORT_4_CTRL_15 0xE3 498e66f840cSTristram Ha #define REG_PORT_5_CTRL_15 0xF3 499e66f840cSTristram Ha #define REG_PORT_1_CTRL_16 0xB4 500e66f840cSTristram Ha #define REG_PORT_2_CTRL_16 0xC4 501e66f840cSTristram Ha #define REG_PORT_3_CTRL_16 0xD4 502e66f840cSTristram Ha #define REG_PORT_4_CTRL_16 0xE4 503e66f840cSTristram Ha #define REG_PORT_5_CTRL_16 0xF4 504e66f840cSTristram Ha #define REG_PORT_1_CTRL_17 0xB5 505e66f840cSTristram Ha #define REG_PORT_2_CTRL_17 0xC5 506e66f840cSTristram Ha #define REG_PORT_3_CTRL_17 0xD5 507e66f840cSTristram Ha #define REG_PORT_4_CTRL_17 0xE5 508e66f840cSTristram Ha #define REG_PORT_5_CTRL_17 0xF5 509e66f840cSTristram Ha 510e66f840cSTristram Ha #define REG_PORT_1_RATE_CTRL_3 0xB2 511e66f840cSTristram Ha #define REG_PORT_1_RATE_CTRL_2 0xB3 512e66f840cSTristram Ha #define REG_PORT_1_RATE_CTRL_1 0xB4 513e66f840cSTristram Ha #define REG_PORT_1_RATE_CTRL_0 0xB5 514e66f840cSTristram Ha #define REG_PORT_2_RATE_CTRL_3 0xC2 515e66f840cSTristram Ha #define REG_PORT_2_RATE_CTRL_2 0xC3 516e66f840cSTristram Ha #define REG_PORT_2_RATE_CTRL_1 0xC4 517e66f840cSTristram Ha #define REG_PORT_2_RATE_CTRL_0 0xC5 518e66f840cSTristram Ha #define REG_PORT_3_RATE_CTRL_3 0xD2 519e66f840cSTristram Ha #define REG_PORT_3_RATE_CTRL_2 0xD3 520e66f840cSTristram Ha #define REG_PORT_3_RATE_CTRL_1 0xD4 521e66f840cSTristram Ha #define REG_PORT_3_RATE_CTRL_0 0xD5 522e66f840cSTristram Ha #define REG_PORT_4_RATE_CTRL_3 0xE2 523e66f840cSTristram Ha #define REG_PORT_4_RATE_CTRL_2 0xE3 524e66f840cSTristram Ha #define REG_PORT_4_RATE_CTRL_1 0xE4 525e66f840cSTristram Ha #define REG_PORT_4_RATE_CTRL_0 0xE5 526e66f840cSTristram Ha #define REG_PORT_5_RATE_CTRL_3 0xF2 527e66f840cSTristram Ha #define REG_PORT_5_RATE_CTRL_2 0xF3 528e66f840cSTristram Ha #define REG_PORT_5_RATE_CTRL_1 0xF4 529e66f840cSTristram Ha #define REG_PORT_5_RATE_CTRL_0 0xF5 530e66f840cSTristram Ha 531e66f840cSTristram Ha #define RATE_CTRL_ENABLE BIT(7) 532e66f840cSTristram Ha #define RATE_RATIO_M (BIT(7) - 1) 533e66f840cSTristram Ha 534e66f840cSTristram Ha #define PORT_OUT_RATE_ENABLE BIT(7) 535e66f840cSTristram Ha 536e66f840cSTristram Ha #define REG_PORT_1_RATE_LIMIT 0xB6 537e66f840cSTristram Ha #define REG_PORT_2_RATE_LIMIT 0xC6 538e66f840cSTristram Ha #define REG_PORT_3_RATE_LIMIT 0xD6 539e66f840cSTristram Ha #define REG_PORT_4_RATE_LIMIT 0xE6 540e66f840cSTristram Ha #define REG_PORT_5_RATE_LIMIT 0xF6 541e66f840cSTristram Ha 542e66f840cSTristram Ha #define PORT_IN_PORT_BASED_S 6 543e66f840cSTristram Ha #define PORT_RATE_PACKET_BASED_S 5 544e66f840cSTristram Ha #define PORT_IN_FLOW_CTRL_S 4 545e66f840cSTristram Ha #define PORT_IN_LIMIT_MODE_M 0x3 546e66f840cSTristram Ha #define PORT_IN_LIMIT_MODE_S 2 547e66f840cSTristram Ha #define PORT_COUNT_IFG_S 1 548e66f840cSTristram Ha #define PORT_COUNT_PREAMBLE_S 0 549e66f840cSTristram Ha #define PORT_IN_PORT_BASED BIT(PORT_IN_PORT_BASED_S) 550e66f840cSTristram Ha #define PORT_RATE_PACKET_BASED BIT(PORT_RATE_PACKET_BASED_S) 551e66f840cSTristram Ha #define PORT_IN_FLOW_CTRL BIT(PORT_IN_FLOW_CTRL_S) 552e66f840cSTristram Ha #define PORT_IN_ALL 0 553e66f840cSTristram Ha #define PORT_IN_UNICAST 1 554e66f840cSTristram Ha #define PORT_IN_MULTICAST 2 555e66f840cSTristram Ha #define PORT_IN_BROADCAST 3 556e66f840cSTristram Ha #define PORT_COUNT_IFG BIT(PORT_COUNT_IFG_S) 557e66f840cSTristram Ha #define PORT_COUNT_PREAMBLE BIT(PORT_COUNT_PREAMBLE_S) 558e66f840cSTristram Ha 559e66f840cSTristram Ha #define REG_PORT_1_IN_RATE_0 0xB7 560e66f840cSTristram Ha #define REG_PORT_2_IN_RATE_0 0xC7 561e66f840cSTristram Ha #define REG_PORT_3_IN_RATE_0 0xD7 562e66f840cSTristram Ha #define REG_PORT_4_IN_RATE_0 0xE7 563e66f840cSTristram Ha #define REG_PORT_5_IN_RATE_0 0xF7 564e66f840cSTristram Ha #define REG_PORT_1_IN_RATE_1 0xB8 565e66f840cSTristram Ha #define REG_PORT_2_IN_RATE_1 0xC8 566e66f840cSTristram Ha #define REG_PORT_3_IN_RATE_1 0xD8 567e66f840cSTristram Ha #define REG_PORT_4_IN_RATE_1 0xE8 568e66f840cSTristram Ha #define REG_PORT_5_IN_RATE_1 0xF8 569e66f840cSTristram Ha #define REG_PORT_1_IN_RATE_2 0xB9 570e66f840cSTristram Ha #define REG_PORT_2_IN_RATE_2 0xC9 571e66f840cSTristram Ha #define REG_PORT_3_IN_RATE_2 0xD9 572e66f840cSTristram Ha #define REG_PORT_4_IN_RATE_2 0xE9 573e66f840cSTristram Ha #define REG_PORT_5_IN_RATE_2 0xF9 574e66f840cSTristram Ha #define REG_PORT_1_IN_RATE_3 0xBA 575e66f840cSTristram Ha #define REG_PORT_2_IN_RATE_3 0xCA 576e66f840cSTristram Ha #define REG_PORT_3_IN_RATE_3 0xDA 577e66f840cSTristram Ha #define REG_PORT_4_IN_RATE_3 0xEA 578e66f840cSTristram Ha #define REG_PORT_5_IN_RATE_3 0xFA 579e66f840cSTristram Ha 580e66f840cSTristram Ha #define PORT_IN_RATE_ENABLE BIT(7) 581e66f840cSTristram Ha #define PORT_RATE_LIMIT_M (BIT(7) - 1) 582e66f840cSTristram Ha 583e66f840cSTristram Ha #define REG_PORT_1_OUT_RATE_0 0xBB 584e66f840cSTristram Ha #define REG_PORT_2_OUT_RATE_0 0xCB 585e66f840cSTristram Ha #define REG_PORT_3_OUT_RATE_0 0xDB 586e66f840cSTristram Ha #define REG_PORT_4_OUT_RATE_0 0xEB 587e66f840cSTristram Ha #define REG_PORT_5_OUT_RATE_0 0xFB 588e66f840cSTristram Ha #define REG_PORT_1_OUT_RATE_1 0xBC 589e66f840cSTristram Ha #define REG_PORT_2_OUT_RATE_1 0xCC 590e66f840cSTristram Ha #define REG_PORT_3_OUT_RATE_1 0xDC 591e66f840cSTristram Ha #define REG_PORT_4_OUT_RATE_1 0xEC 592e66f840cSTristram Ha #define REG_PORT_5_OUT_RATE_1 0xFC 593e66f840cSTristram Ha #define REG_PORT_1_OUT_RATE_2 0xBD 594e66f840cSTristram Ha #define REG_PORT_2_OUT_RATE_2 0xCD 595e66f840cSTristram Ha #define REG_PORT_3_OUT_RATE_2 0xDD 596e66f840cSTristram Ha #define REG_PORT_4_OUT_RATE_2 0xED 597e66f840cSTristram Ha #define REG_PORT_5_OUT_RATE_2 0xFD 598e66f840cSTristram Ha #define REG_PORT_1_OUT_RATE_3 0xBE 599e66f840cSTristram Ha #define REG_PORT_2_OUT_RATE_3 0xCE 600e66f840cSTristram Ha #define REG_PORT_3_OUT_RATE_3 0xDE 601e66f840cSTristram Ha #define REG_PORT_4_OUT_RATE_3 0xEE 602e66f840cSTristram Ha #define REG_PORT_5_OUT_RATE_3 0xFE 603e66f840cSTristram Ha 604ef3b02a1SBen Hutchings /* 88x3 specific */ 605ef3b02a1SBen Hutchings 606ef3b02a1SBen Hutchings #define REG_SW_INSERT_SRC_PVID 0xC2 607ef3b02a1SBen Hutchings 608e66f840cSTristram Ha /* PME */ 609e66f840cSTristram Ha 610e66f840cSTristram Ha #define SW_PME_OUTPUT_ENABLE BIT(1) 611e66f840cSTristram Ha #define SW_PME_ACTIVE_HIGH BIT(0) 612e66f840cSTristram Ha 613e66f840cSTristram Ha #define PORT_MAGIC_PACKET_DETECT BIT(2) 614e66f840cSTristram Ha #define PORT_LINK_UP_DETECT BIT(1) 615e66f840cSTristram Ha #define PORT_ENERGY_DETECT BIT(0) 616e66f840cSTristram Ha 617e66f840cSTristram Ha /* ACL */ 618e66f840cSTristram Ha 619e66f840cSTristram Ha #define ACL_FIRST_RULE_M 0xF 620e66f840cSTristram Ha 621e66f840cSTristram Ha #define ACL_MODE_M 0x3 622e66f840cSTristram Ha #define ACL_MODE_S 4 623e66f840cSTristram Ha #define ACL_MODE_DISABLE 0 624e66f840cSTristram Ha #define ACL_MODE_LAYER_2 1 625e66f840cSTristram Ha #define ACL_MODE_LAYER_3 2 626e66f840cSTristram Ha #define ACL_MODE_LAYER_4 3 627e66f840cSTristram Ha #define ACL_ENABLE_M 0x3 628e66f840cSTristram Ha #define ACL_ENABLE_S 2 629e66f840cSTristram Ha #define ACL_ENABLE_2_COUNT 0 630e66f840cSTristram Ha #define ACL_ENABLE_2_TYPE 1 631e66f840cSTristram Ha #define ACL_ENABLE_2_MAC 2 632e66f840cSTristram Ha #define ACL_ENABLE_2_BOTH 3 633e66f840cSTristram Ha #define ACL_ENABLE_3_IP 1 634e66f840cSTristram Ha #define ACL_ENABLE_3_SRC_DST_COMP 2 635e66f840cSTristram Ha #define ACL_ENABLE_4_PROTOCOL 0 636e66f840cSTristram Ha #define ACL_ENABLE_4_TCP_PORT_COMP 1 637e66f840cSTristram Ha #define ACL_ENABLE_4_UDP_PORT_COMP 2 638e66f840cSTristram Ha #define ACL_ENABLE_4_TCP_SEQN_COMP 3 639e66f840cSTristram Ha #define ACL_SRC BIT(1) 640e66f840cSTristram Ha #define ACL_EQUAL BIT(0) 641e66f840cSTristram Ha 642e66f840cSTristram Ha #define ACL_MAX_PORT 0xFFFF 643e66f840cSTristram Ha 644e66f840cSTristram Ha #define ACL_MIN_PORT 0xFFFF 645e66f840cSTristram Ha #define ACL_IP_ADDR 0xFFFFFFFF 646e66f840cSTristram Ha #define ACL_TCP_SEQNUM 0xFFFFFFFF 647e66f840cSTristram Ha 648e66f840cSTristram Ha #define ACL_RESERVED 0xF8 649e66f840cSTristram Ha #define ACL_PORT_MODE_M 0x3 650e66f840cSTristram Ha #define ACL_PORT_MODE_S 1 651e66f840cSTristram Ha #define ACL_PORT_MODE_DISABLE 0 652e66f840cSTristram Ha #define ACL_PORT_MODE_EITHER 1 653e66f840cSTristram Ha #define ACL_PORT_MODE_IN_RANGE 2 654e66f840cSTristram Ha #define ACL_PORT_MODE_OUT_OF_RANGE 3 655e66f840cSTristram Ha 656e66f840cSTristram Ha #define ACL_TCP_FLAG_ENABLE BIT(0) 657e66f840cSTristram Ha 658e66f840cSTristram Ha #define ACL_TCP_FLAG_M 0xFF 659e66f840cSTristram Ha 660e66f840cSTristram Ha #define ACL_TCP_FLAG 0xFF 661e66f840cSTristram Ha #define ACL_ETH_TYPE 0xFFFF 662e66f840cSTristram Ha #define ACL_IP_M 0xFFFFFFFF 663e66f840cSTristram Ha 664e66f840cSTristram Ha #define ACL_PRIO_MODE_M 0x3 665e66f840cSTristram Ha #define ACL_PRIO_MODE_S 6 666e66f840cSTristram Ha #define ACL_PRIO_MODE_DISABLE 0 667e66f840cSTristram Ha #define ACL_PRIO_MODE_HIGHER 1 668e66f840cSTristram Ha #define ACL_PRIO_MODE_LOWER 2 669e66f840cSTristram Ha #define ACL_PRIO_MODE_REPLACE 3 670e66f840cSTristram Ha #define ACL_PRIO_M 0x7 671e66f840cSTristram Ha #define ACL_PRIO_S 3 672e66f840cSTristram Ha #define ACL_VLAN_PRIO_REPLACE BIT(2) 673e66f840cSTristram Ha #define ACL_VLAN_PRIO_M 0x7 674e66f840cSTristram Ha #define ACL_VLAN_PRIO_HI_M 0x3 675e66f840cSTristram Ha 676e66f840cSTristram Ha #define ACL_VLAN_PRIO_LO_M 0x8 677e66f840cSTristram Ha #define ACL_VLAN_PRIO_S 7 678e66f840cSTristram Ha #define ACL_MAP_MODE_M 0x3 679e66f840cSTristram Ha #define ACL_MAP_MODE_S 5 680e66f840cSTristram Ha #define ACL_MAP_MODE_DISABLE 0 681e66f840cSTristram Ha #define ACL_MAP_MODE_OR 1 682e66f840cSTristram Ha #define ACL_MAP_MODE_AND 2 683e66f840cSTristram Ha #define ACL_MAP_MODE_REPLACE 3 684e66f840cSTristram Ha #define ACL_MAP_PORT_M 0x1F 685e66f840cSTristram Ha 686e66f840cSTristram Ha #define ACL_CNT_M (BIT(11) - 1) 687e66f840cSTristram Ha #define ACL_CNT_S 5 688e66f840cSTristram Ha #define ACL_MSEC_UNIT BIT(4) 689e66f840cSTristram Ha #define ACL_INTR_MODE BIT(3) 690e66f840cSTristram Ha 691e66f840cSTristram Ha #define REG_PORT_ACL_BYTE_EN_MSB 0x10 692e66f840cSTristram Ha 693e66f840cSTristram Ha #define ACL_BYTE_EN_MSB_M 0x3F 694e66f840cSTristram Ha 695e66f840cSTristram Ha #define REG_PORT_ACL_BYTE_EN_LSB 0x11 696e66f840cSTristram Ha 697e66f840cSTristram Ha #define ACL_ACTION_START 0xA 698e66f840cSTristram Ha #define ACL_ACTION_LEN 2 699e66f840cSTristram Ha #define ACL_INTR_CNT_START 0xB 700e66f840cSTristram Ha #define ACL_RULESET_START 0xC 701e66f840cSTristram Ha #define ACL_RULESET_LEN 2 702e66f840cSTristram Ha #define ACL_TABLE_LEN 14 703e66f840cSTristram Ha 704e66f840cSTristram Ha #define ACL_ACTION_ENABLE 0x000C 705e66f840cSTristram Ha #define ACL_MATCH_ENABLE 0x1FF0 706e66f840cSTristram Ha #define ACL_RULESET_ENABLE 0x2003 707e66f840cSTristram Ha #define ACL_BYTE_ENABLE ((ACL_BYTE_EN_MSB_M << 8) | 0xFF) 708e66f840cSTristram Ha #define ACL_MODE_ENABLE (0x10 << 8) 709e66f840cSTristram Ha 710e66f840cSTristram Ha #define REG_PORT_ACL_CTRL_0 0x12 711e66f840cSTristram Ha 712e66f840cSTristram Ha #define PORT_ACL_WRITE_DONE BIT(6) 713e66f840cSTristram Ha #define PORT_ACL_READ_DONE BIT(5) 714e66f840cSTristram Ha #define PORT_ACL_WRITE BIT(4) 715e66f840cSTristram Ha #define PORT_ACL_INDEX_M 0xF 716e66f840cSTristram Ha 717e66f840cSTristram Ha #define REG_PORT_ACL_CTRL_1 0x13 718e66f840cSTristram Ha 719e66f840cSTristram Ha #define PORT_ACL_FORCE_DLR_MISS BIT(0) 720e66f840cSTristram Ha 721e66f840cSTristram Ha #define KSZ8795_ID_HI 0x0022 722e66f840cSTristram Ha #define KSZ8795_ID_LO 0x1550 7234b20a07eSOleksij Rempel #define KSZ8863_ID_LO 0x1430 724e66f840cSTristram Ha 725e66f840cSTristram Ha #define KSZ8795_SW_ID 0x8795 726e66f840cSTristram Ha 727e66f840cSTristram Ha #define PHY_REG_LINK_MD 0x1D 728e66f840cSTristram Ha 729e66f840cSTristram Ha #define PHY_START_CABLE_DIAG BIT(15) 73036838050SOleksij Rempel #define PHY_CABLE_DIAG_RESULT_M GENMASK(14, 13) 731e66f840cSTristram Ha #define PHY_CABLE_DIAG_RESULT 0x6000 732e66f840cSTristram Ha #define PHY_CABLE_STAT_NORMAL 0x0000 733e66f840cSTristram Ha #define PHY_CABLE_STAT_OPEN 0x2000 734e66f840cSTristram Ha #define PHY_CABLE_STAT_SHORT 0x4000 735e66f840cSTristram Ha #define PHY_CABLE_STAT_FAILED 0x6000 736e66f840cSTristram Ha #define PHY_CABLE_10M_SHORT BIT(12) 73736838050SOleksij Rempel #define PHY_CABLE_FAULT_COUNTER_M GENMASK(8, 0) 738e66f840cSTristram Ha 739e66f840cSTristram Ha #define PHY_REG_PHY_CTRL 0x1F 740e66f840cSTristram Ha 741e66f840cSTristram Ha #define PHY_MODE_M 0x7 742e66f840cSTristram Ha #define PHY_MODE_S 8 743e66f840cSTristram Ha #define PHY_STAT_REVERSED_POLARITY BIT(5) 744e66f840cSTristram Ha #define PHY_STAT_MDIX BIT(4) 745e66f840cSTristram Ha #define PHY_FORCE_LINK BIT(3) 746e66f840cSTristram Ha #define PHY_POWER_SAVING_ENABLE BIT(2) 747e66f840cSTristram Ha #define PHY_REMOTE_LOOPBACK BIT(1) 748e66f840cSTristram Ha 749e66f840cSTristram Ha /* Chip resource */ 750e66f840cSTristram Ha 751e66f840cSTristram Ha #define PRIO_QUEUES 4 752e66f840cSTristram Ha 753e66f840cSTristram Ha #define KS_PRIO_IN_REG 4 754e66f840cSTristram Ha 7554b20a07eSOleksij Rempel #define MIB_COUNTER_NUM 0x20 756e66f840cSTristram Ha 757e66f840cSTristram Ha /* Common names used by other drivers */ 758e66f840cSTristram Ha 759e66f840cSTristram Ha #define P_BCAST_STORM_CTRL REG_PORT_CTRL_0 760e66f840cSTristram Ha #define P_PRIO_CTRL REG_PORT_CTRL_0 761e66f840cSTristram Ha #define P_TAG_CTRL REG_PORT_CTRL_0 762e66f840cSTristram Ha #define P_MIRROR_CTRL REG_PORT_CTRL_1 763e66f840cSTristram Ha #define P_802_1P_CTRL REG_PORT_CTRL_2 764e66f840cSTristram Ha #define P_PASS_ALL_CTRL REG_PORT_CTRL_12 765e66f840cSTristram Ha #define P_INS_SRC_PVID_CTRL REG_PORT_CTRL_12 766e66f840cSTristram Ha #define P_DROP_TAG_CTRL REG_PORT_CTRL_13 767e66f840cSTristram Ha #define P_RATE_LIMIT_CTRL REG_PORT_RATE_LIMIT 768e66f840cSTristram Ha 769e66f840cSTristram Ha #define S_UNKNOWN_DA_CTRL REG_SWITCH_CTRL_12 770e66f840cSTristram Ha #define S_FORWARD_INVALID_VID_CTRL REG_FORWARD_INVALID_VID 771e66f840cSTristram Ha 772e66f840cSTristram Ha #define S_FLUSH_TABLE_CTRL REG_SW_CTRL_0 773e66f840cSTristram Ha #define S_LINK_AGING_CTRL REG_SW_CTRL_0 774e66f840cSTristram Ha #define S_HUGE_PACKET_CTRL REG_SW_CTRL_1 775e66f840cSTristram Ha #define S_MIRROR_CTRL REG_SW_CTRL_3 776e66f840cSTristram Ha #define S_REPLACE_VID_CTRL REG_SW_CTRL_4 777e66f840cSTristram Ha #define S_PASS_PAUSE_CTRL REG_SW_CTRL_10 778e66f840cSTristram Ha #define S_802_1P_PRIO_CTRL REG_SW_CTRL_12 779e66f840cSTristram Ha #define S_TOS_PRIO_CTRL REG_TOS_PRIO_CTRL_0 780e66f840cSTristram Ha #define S_IPV6_MLD_CTRL REG_SW_CTRL_21 781e66f840cSTristram Ha 782e66f840cSTristram Ha #define IND_ACC_TABLE(table) ((table) << 8) 783e66f840cSTristram Ha 7847b6e6235SOleksij Rempel /* */ 7857b6e6235SOleksij Rempel #define REG_IND_EEE_GLOB2_LO 0x34 7867b6e6235SOleksij Rempel #define REG_IND_EEE_GLOB2_HI 0x35 7877b6e6235SOleksij Rempel 788e66f840cSTristram Ha /** 789e66f840cSTristram Ha * MIB_COUNTER_VALUE 00-00000000-3FFFFFFF 790e66f840cSTristram Ha * MIB_TOTAL_BYTES 00-0000000F-FFFFFFFF 791e66f840cSTristram Ha * MIB_PACKET_DROPPED 00-00000000-0000FFFF 792e66f840cSTristram Ha * MIB_COUNTER_VALID 00-00000020-00000000 793e66f840cSTristram Ha * MIB_COUNTER_OVERFLOW 00-00000040-00000000 794e66f840cSTristram Ha */ 795e66f840cSTristram Ha 796e66f840cSTristram Ha #define MIB_COUNTER_VALUE 0x3FFFFFFF 797e66f840cSTristram Ha 7984b20a07eSOleksij Rempel #define KSZ8795_MIB_TOTAL_RX_0 0x100 7994b20a07eSOleksij Rempel #define KSZ8795_MIB_TOTAL_TX_0 0x101 8004b20a07eSOleksij Rempel #define KSZ8795_MIB_TOTAL_RX_1 0x104 8014b20a07eSOleksij Rempel #define KSZ8795_MIB_TOTAL_TX_1 0x105 8024b20a07eSOleksij Rempel 8034b20a07eSOleksij Rempel #define KSZ8863_MIB_PACKET_DROPPED_TX_0 0x100 8044b20a07eSOleksij Rempel #define KSZ8863_MIB_PACKET_DROPPED_RX_0 0x105 805e66f840cSTristram Ha 806e66f840cSTristram Ha #define MIB_PACKET_DROPPED 0x0000FFFF 807e66f840cSTristram Ha 808e66f840cSTristram Ha #define MIB_TOTAL_BYTES_H 0x0000000F 809e66f840cSTristram Ha 810e66f840cSTristram Ha #define TAIL_TAG_OVERRIDE BIT(6) 811e66f840cSTristram Ha #define TAIL_TAG_LOOKUP BIT(7) 812e66f840cSTristram Ha 813e66f840cSTristram Ha #define FID_ENTRIES 128 814e66f840cSTristram Ha 815e66f840cSTristram Ha #endif 816