| /openbmc/linux/drivers/staging/vt6655/ |
| H A D | rf.c | 55 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
56 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
57 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
58 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
59 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
60 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
61 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
62 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
63 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
64 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
[all …]
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| /openbmc/linux/arch/powerpc/boot/dts/ |
| H A D | ac14xx.dts | 26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
145 bus-frequency = <80000000>; /* 80 MHz ips bus */
174 at24@30 {
262 54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10
263 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D5];
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| /openbmc/u-boot/arch/arm/include/asm/arch-s32v234/ |
| H A D | mc_cgm_regs.h | 97 #define PLLDIG_PLLFD_SMDEN (1 << 30)
178 /* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */
182 /* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */
186 /* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */
199 #define PERIPH_PLL_PLLDV_MFD (30)
204 /* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/
208 /* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/
212 /* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/
216 /* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/
227 /* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */
[all …]
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| /openbmc/qemu/include/hw/misc/ |
| H A D | aspeed_scu.h | 100 * 30:28 Video Engine clock slow down setting
131 * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)]
148 * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
150 * The default frequency is 792Mhz when CLKIN = 24MHz
162 * 23 Enable 25 MHz reference clock input
264 * 30 Enable GPIO Strap Mode
271 * 23 Select 25 MHz reference clock input mode
293 #define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30)
345 * (Output frequency) = CLKIN(25MHz) * [(M+1) / (N+1)] / (P+1)
347 * The default frequency is 1200Mhz when CLKIN = 25MHz
[all …]
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-tps68470.c | 41 * frequency range of 3 MHz to 27 MHz by a programmable
44 * of 4 MHz to 64 MHz in increments of 0.1 MHz.
46 * hclk_# = osc_in * (((plldiv*2)+320) / (xtaldiv+30)) * (1 / 2^postdiv)
49 * PLL_REF_CLK = input clk / XTALDIV[7:0] + 30)
53 * BOOST should be as close as possible to 2Mhz
56 * BUCK should be as close as possible to 5.2Mhz
60 * 20Mhz 170 32 1 19.2Mhz
61 * 20Mhz 170 40 1 20Mhz
62 * 20Mhz 170 80 1 24Mhz
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| H A D | clk-gemini.c | 29 #define PLL_OSC_SEL BIT(30)
134 /* We support 33 and 66 MHz */ in gemini_pci_round_rate()
228 /* Manual says to always set BIT 30 (CPU1) to 1 */ in gemini_reset()
353 * This clock is supposed to be 27MHz as this is an exact multiple in gemini_clk_probe()
432 * XTAL is the crystal oscillator, 60 or 30 MHz selected from in gemini_cc_init()
440 pr_debug("main crystal @%lu MHz\n", freq / 1000000); in gemini_cc_init()
445 /* If we run on 30 MHz crystal we have to multiply with two */ in gemini_cc_init()
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| /openbmc/linux/include/linux/mfd/ |
| H A D | si476x-platform.h | 72 SI476X_ICIN_IC_LINK = 30,
80 SI476X_ICIP_IC_LINK = 30,
87 SI476X_ICON_IC_LINK = 30,
94 SI476X_ICOP_IC_LINK = 30,
202 * SI476X_XTAL_37P209375_MHZ - 37.209375 Mhz
203 * SI476X_XTAL_36P4_MHZ - 36.4 Mhz
204 * SI476X_XTAL_37P8_MHZ - 37.8 Mhz
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| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | s5h1432.c | 90 /* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2 */ in s5h1432_set_channel_bandwidth()
199 msleep(30); in s5h1432_set_frontend()
201 msleep(30); in s5h1432_set_frontend()
223 msleep(30); in s5h1432_set_frontend()
225 msleep(30); in s5h1432_set_frontend()
269 /*Set 3.3MHz as default IF frequency */ in s5h1432_init()
285 msleep(30); in s5h1432_init()
364 .frequency_min_hz = 177 * MHz,
365 .frequency_max_hz = 858 * MHz,
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| /openbmc/u-boot/board/renesas/r2dplus/ |
| H A D | lowlevel_init.S | 3 * Initial Register Data for R0P751RLC0011RL (SH7751R 240MHz/120MHz/60MHz)
52 /* Wait DRAM refresh 30 times */
54 mov #30, r3
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| /openbmc/linux/drivers/watchdog/ |
| H A D | sc520_wdt.c | 84 * char to /dev/watchdog every 30 seconds.
87 #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */
108 #define WDT_EXP_SEL_01 0x0001 /* [01] Time-out = 496 us (with 33 Mhz clk). */
109 #define WDT_EXP_SEL_02 0x0002 /* [02] Time-out = 508 ms (with 33 Mhz clk). */
110 #define WDT_EXP_SEL_03 0x0004 /* [03] Time-out = 1.02 s (with 33 Mhz clk). */
111 #define WDT_EXP_SEL_04 0x0008 /* [04] Time-out = 2.03 s (with 33 Mhz clk). */
112 #define WDT_EXP_SEL_05 0x0010 /* [05] Time-out = 4.07 s (with 33 Mhz clk). */
113 #define WDT_EXP_SEL_06 0x0020 /* [06] Time-out = 8.13 s (with 33 Mhz clk). */
114 #define WDT_EXP_SEL_07 0x0040 /* [07] Time-out = 16.27s (with 33 Mhz clk). */
115 #define WDT_EXP_SEL_08 0x0080 /* [08] Time-out = 32.54s (with 33 Mhz clk). */
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| H A D | aspeed_wdt.c | 103 * and bit 30 represents push-pull or open-drain. With respect to write, magic
113 #define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
119 /* 32 bits at 1MHz, in milliseconds */
121 #define WDT_DEFAULT_TIMEOUT 30
360 * - ast2400 wdt can run at PCLK, or 1MHz in aspeed_wdt_probe()
361 * - ast2500 only runs at 1MHz, hard coding bit 4 to 1 in aspeed_wdt_probe()
362 * - ast2600 always runs at 1MHz in aspeed_wdt_probe()
364 * Set the ast2400 to run at 1MHz as it simplifies the driver. in aspeed_wdt_probe()
399 * Primarily, ensure we're using the 1MHz clock source. in aspeed_wdt_probe()
447 * The watchdog is always configured with a 1MHz source, so in aspeed_wdt_probe()
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| /openbmc/linux/drivers/net/wireless/ath/ath10k/ |
| H A D | rx_desc.h | 44 RX_ATTENTION_FLAGS_FCS_ERR = BIT(30),
371 #define RX_MPDU_END_INFO0_DECRYPT_ERR BIT(30)
586 #define RX_MSDU_END_INFO0_PRE_DELIM_ERR BIT(30)
767 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
771 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
775 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
779 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
783 * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
787 * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth.
791 * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth.
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | rockchip,dwc3.yaml | 54 Controller reference clock, must to be 24 MHz
56 Controller suspend clock, must to be 24 MHz or 32 KHz
58 Master/Core clock, must to be >= 62.5 MHz for SS
59 operation and >= 30MHz for HS operation
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| H A D | rockchip,rk3399-dwc3.yaml | 27 Controller reference clock, must to be 24 MHz
29 Controller suspend clock, must to be 24 MHz or 32 KHz
31 Master/Core clock, must to be >= 62.5 MHz for SS
32 operation and >= 30MHz for HS operation
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| /openbmc/linux/drivers/clk/ingenic/ |
| H A D | jz4760-cgu.c | 20 #define MHZ (1000 * 1000) macro
63 /* The frequency after the N divider must be between 1 and 50 MHz. */ in jz4760_cgu_calc_m_n_od()
64 n = parent_rate / (1 * MHZ); in jz4760_cgu_calc_m_n_od()
69 rate /= MHZ; in jz4760_cgu_calc_m_n_od()
70 parent_rate /= MHZ; in jz4760_cgu_calc_m_n_od()
243 .mux = { CGU_REG_LPCDR, 30, 1 },
260 .mux = { CGU_REG_PCMCDR, 30, 2 },
268 .mux = { CGU_REG_I2SCDR, 30, 2 },
275 .mux = { CGU_REG_USBCDR, 30, 2 },
382 .gate = { CGU_REG_LCR, 30, false, 150 },
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| /openbmc/u-boot/arch/mips/mach-ath79/ar934x/ |
| H A D | clk.c | 20 * XTAL [MHz] 2^(18 - 1)
21 * PLL [MHz] = ------------ * ----------------------
33 /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
87 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
89 setbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
94 clrbits_be32(pll_reg_base + 0x8, BIT(30)); in ar934x_srif_pll_cfg()
120 /* Test for 40MHz XTAL */ in ar934x_pll_init()
323 printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000); in do_ar934x_showclk()
324 printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000); in do_ar934x_showclk()
325 printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000); in do_ar934x_showclk()
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| /openbmc/u-boot/board/creative/xfi3/ |
| H A D | xfi3.c | 28 /* IO0 clock at 480MHz */ in board_early_init_f()
31 /* SSP0 clock at 96MHz */ in board_early_init_f()
126 { 0x21, 30, 0x0000 },
127 /* Wait 30 mS here */
129 { 0x11, 30, 0x1038 },
130 /* Wait 30 mS here */
153 { 0x59, 30, 0x0a09 },
154 /* Wait 30 mS here */
155 { 0x07, 30, 0x1017 },
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| /openbmc/u-boot/arch/arm/include/asm/arch-imx8/sci/ |
| H A D | types.h | 21 #define SC_10MHZ 10000000U /* 10MHz */
22 #define SC_20MHZ 20000000U /* 20MHz */
23 #define SC_25MHZ 25000000U /* 25MHz */
24 #define SC_27MHZ 27000000U /* 27MHz */
25 #define SC_40MHZ 40000000U /* 40MHz */
26 #define SC_45MHZ 45000000U /* 45MHz */
27 #define SC_50MHZ 50000000U /* 50MHz */
28 #define SC_60MHZ 60000000U /* 60MHz */
29 #define SC_66MHZ 66666666U /* 66MHz */
30 #define SC_74MHZ 74250000U /* 74.25MHz */
[all …]
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| /openbmc/linux/drivers/clk/mvebu/ |
| H A D | dove.c | 26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
35 * 14 = 400 MHz
[all …]
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| H A D | armada-375.c | 29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
172 { "crypto1_enc", NULL, 30 },
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| /openbmc/u-boot/board/samsung/goni/ |
| H A D | lowlevel_init.S | 155 ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
210 ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
257 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
260 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
263 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
312 ldr r1, =0x2cf @ Locktime : 30us
320 ldr r1, =0x80C80601 @ 800MHz
323 ldr r1, =0x829B0C01 @ 667MHz
326 ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
329 ldr r1, =0x806C0603 @ 54MHz
[all …]
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| /openbmc/linux/drivers/net/wireless/intel/iwlwifi/cfg/ |
| H A D | 9000.c | 16 #define IWL9000_UCODE_API_MIN 30
163 const char iwl9162_160_name[] = "Intel(R) Wireless-AC 9162 160MHz";
164 const char iwl9260_160_name[] = "Intel(R) Wireless-AC 9260 160MHz";
165 const char iwl9270_160_name[] = "Intel(R) Wireless-AC 9270 160MHz";
166 const char iwl9461_160_name[] = "Intel(R) Wireless-AC 9461 160MHz";
167 const char iwl9462_160_name[] = "Intel(R) Wireless-AC 9462 160MHz";
168 const char iwl9560_160_name[] = "Intel(R) Wireless-AC 9560 160MHz";
171 "Killer (R) Wireless-AC 1550 Wireless Network Adapter (9260NGW) 160MHz";
175 "Killer(R) Wireless-AC 1550i Wireless Network Adapter (9560NGW) 160MHz";
179 "Killer(R) Wireless-AC 1550s Wireless Network Adapter (9560D2W) 160MHz";
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| /openbmc/linux/drivers/video/fbdev/ |
| H A D | valkyriefb.h | 79 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
154 { 25, 32, 3 }, /* pixel clock = 40.0015MHz,
155 used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
163 { 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
[all …]
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| /openbmc/linux/drivers/mmc/host/ |
| H A D | sdhci-of-arasan.c | 203 * met at 25MHz for Default Speed mode, those controllers work at
204 * 19MHz instead
401 * requirements met at 25MHz for Default Speed mode, in sdhci_arasan_set_clock()
402 * those controllers work at 19MHz instead. in sdhci_arasan_set_clock()
751 /* For 50MHz clock, 30 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
752 tap_max = 30; in sdhci_zynqmp_sdcardclk_set_phase()
755 /* For 100MHz clock, 15 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
760 /* For 200MHz clock, 8 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
820 /* For 50MHz clock, 120 Taps are available */ in sdhci_zynqmp_sampleclk_set_phase()
824 /* For 100MHz clock, 60 Taps are available */ in sdhci_zynqmp_sampleclk_set_phase()
[all …]
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| /openbmc/u-boot/board/menlo/m53menlo/ |
| H A D | m53menlo.c | 54 mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); in dram_init()
55 mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); in dram_init()
200 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to in enable_lvds_clock()
201 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 . in enable_lvds_clock()
222 * Set LVDS clock to 9 MHz for the display. The PLL4 is set to in enable_lvds_etm0430g0dh6()
223 * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 . in enable_lvds_etm0430g0dh6()
231 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to in enable_lvds_etm0700g0dh6()
232 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 . in enable_lvds_etm0700g0dh6()
298 .pixclock = 111111, /* picosecond (9 MHz) */
319 .pixclock = 30048, /* picosecond (33.28 MHz) */
[all …]
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