Lines Matching +full:30 +full:mhz

54 	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);  in dram_init()
55 	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);  in dram_init()
200 	 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to  in enable_lvds_clock()
201 	 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .  in enable_lvds_clock()
222 	 * Set LVDS clock to 9 MHz for the display. The PLL4 is set to  in enable_lvds_etm0430g0dh6()
223 	 * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .  in enable_lvds_etm0430g0dh6()
231 	 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to  in enable_lvds_etm0700g0dh6()
232 	 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .  in enable_lvds_etm0700g0dh6()
298 			.pixclock	= 111111, /* picosecond (9 MHz) */
319 			.pixclock	= 30048, /* picosecond (33.28 MHz) */
431 	/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */  in m53_set_clock()
478 	/* NAND clock @ 33MHz */  in board_early_init_f()