Lines Matching +full:30 +full:mhz

97 #define PLLDIG_PLLFD_SMDEN				(1 << 30)
178 /* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */
182 /* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */
186 /* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */
199 #define PERIPH_PLL_PLLDV_MFD		(30)
204 /* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/
208 /* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/
212 /* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/
216 /* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/
227 /* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */
231 /* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */
235 /* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */
248 #define VIDEO_PLL_PLLDV_MFD			(30)