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/openbmc/openbmc/poky/scripts/pybootchartgui/pybootchartgui/
H A Ddraw.py208 def draw_label_in_box(ctx, color, label, x, y, w, maxx): argument
210 label_x = x + w / 2 - label_w / 2
211 if label_w + 10 > w:
212 label_x = x + w + 5
351 w = int ((end - start) * sec_w_base * xscale) + 2 * off_x
371 if w < (720 + off_x):
372 w = 720 + off_x
374 return (w, h)
383 def render_charts(ctx, options, clip, trace, curr_y, w, h, sec_w): argument
390 draw_legend_box(ctx, "CPU (user+sys)", CPU_COLOR, off_x, curr_y+20, leg_s)
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/openbmc/u-boot/lib/
H A Dsha1.c70 unsigned long temp, W[16], A, B, C, D, E; in sha1_process() local
72 GET_UINT32_BE (W[0], data, 0); in sha1_process()
73 GET_UINT32_BE (W[1], data, 4); in sha1_process()
74 GET_UINT32_BE (W[2], data, 8); in sha1_process()
75 GET_UINT32_BE (W[3], data, 12); in sha1_process()
76 GET_UINT32_BE (W[4], data, 16); in sha1_process()
77 GET_UINT32_BE (W[5], data, 20); in sha1_process()
78 GET_UINT32_BE (W[6], data, 24); in sha1_process()
79 GET_UINT32_BE (W[7], data, 28); in sha1_process()
80 GET_UINT32_BE (W[8], data, 32); in sha1_process()
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/openbmc/qemu/hw/sd/
H A Dsdhci-internal.h29 /* R/W SDMA System Address register 0x0 */
32 /* R/W Host DMA Buffer Boundary and Transfer Block Size Register 0x0 */
35 /* R/W Blocks count for current transfer 0x0 */
38 /* R/W Command Argument Register 0x0 */
41 /* R/W Transfer Mode Setting Register 0x0 */
51 /* R/W Command Register 0x0 */
70 /* R/W Buffer Data Register 0x0 */
86 FIELD(SDHC_PRNSTS, DAT_LVL, 20, 4);
91 /* R/W Host control Register 0x0 */
107 /* R/W Power Control Register 0x0 */
[all …]
/openbmc/linux/tools/testing/selftests/net/
H A Dtest_bridge_neigh_suppress.sh17 # | | + eth0.20 | | | + eth0.20 |
36 # | br0.10 br0.20 | | br0.10 br0.20 |
172 ip -n $ns link add link eth0 name eth0.20 up type vlan id 20
175 ip -n $ns address add $v4addr2 dev eth0.20
177 ip -n $ns address add $v6addr2 dev eth0.20
222 ip -n $ns link add link br0 name br0.20 up type vlan id 20
223 bridge -n $ns vlan add vid 20 dev br0 self
227 bridge -n $ns vlan add vid 20 dev swp1
240 bridge -n $ns vlan add vid 20 dev vx0
241 bridge -n $ns vlan add vid 20 dev vx0 tunnel_info id 10020
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H A Dtoeplitz_client.sh6 # This program sends packets periodically for, conservatively, 20 seconds. The
8 # needed, rather than waiting for the 20 second expiration.
11 expiration=$((SECONDS+20))
15 echo "msg $i" | nc "${IPVER}" -u -w 0 "${ADDR}" "${PORT}"
17 echo "msg $i" | nc "${IPVER}" -w 0 "${ADDR}" "${PORT}"
/openbmc/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r1_subq_s_w.c16 "subq_s.w %0, %2, %3\n\t" in main()
21 dsp = (dsp >> 20) & 0x01; in main()
32 "subq_s.w %0, %2, %3\n\t" in main()
37 dsp = (dsp >> 20) & 0x01; in main()
48 "subq_s.w %0, %2, %3\n\t" in main()
53 dsp = (dsp >> 20) & 0x01; in main()
64 "subq_s.w %0, %2, %3\n\t" in main()
69 dsp = (dsp >> 20) & 0x01; in main()
/openbmc/u-boot/cmd/aspeed/nettest/
H A Dmactest.c57 .base_clk_stop = 0x80, .bit_clk_stop = BIT(20),
58 .base_clk_start = 0x84, .bit_clk_start = BIT(20),
67 .base_reset_assert = 0x50, .bit_reset_assert = BIT(20),
68 .base_reset_deassert = 0x54,.bit_reset_deassert = BIT(20),
69 .base_clk_stop = 0x90, .bit_clk_stop = BIT(20),
70 .base_clk_start = 0x94, .bit_clk_start = BIT(20),
86 .base_clk_stop = 0x0c, .bit_clk_stop = BIT(20),
87 .base_clk_start = 0x0c, .bit_clk_start = BIT(20),
135 printf("%20s| 0: NCSI configuration with " in print_arg_test_mode()
137 printf("%20s| (default:%3d)\n", "", DEF_GTESTMODE); in print_arg_test_mode()
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/openbmc/linux/include/linux/soc/ti/
H A Domap1-usb.h24 # define USB2_TRX_MODE(w) (((w)>>24)&0x07) argument
25 # define USB1_TRX_MODE(w) (((w)>>20)&0x07) argument
26 # define USB0_TRX_MODE(w) (((w)>>16)&0x07) argument
38 # define SRP_GPUVBUS(w) (((w)>>24)&0x07) argument
39 # define A_WAIT_VRISE(w) (((w)>>20)&0x07) argument
40 # define B_ASE_BRST(w) (((w)>>16)&0x07) argument
49 # define OTG_HMC(w) (((w)>>0)&0x3f) argument
60 # define OTG_ASESSVLD (1 << 20)
/openbmc/qemu/tests/tcg/multiarch/
H A Dsha1.c44 void SHA1Final(unsigned char digest[20], SHA1_CTX* context);
63 #define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30); argument
64 #define R1(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk(i)+0x5A827999+rol(v,5);w=rol(w,30); argument
65 #define R2(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0x6ED9EBA1+rol(v,5);w=rol(w,30); argument
66 #define R3(v,w,x,y,z,i) z+=(((w|x)&y)|(w&x))+blk(i)+0x8F1BBCDC+rol(v,5);w=rol(w,30); argument
67 #define R4(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0xCA62C1D6+rol(v,5);w=rol(w,30); argument
96 /* 4 rounds of 20 operations each. Loop unrolled. */ in SHA1Transform()
102 R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); in SHA1Transform()
172 void SHA1Final(unsigned char digest[20], SHA1_CTX* context) in SHA1Final() argument
207 for (i = 0; i < 20; i++) { in SHA1Final()
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/openbox/files/
H A D0001-Fix-function-protype-visibility.patch3 Date: Fri, 2 Sep 2022 12:32:20 -0700
23 @@ -20,6 +20,7 @@
42 GtkWidget *w;
50 void desktops_setup_num(GtkWidget *w);
51 void desktops_setup_names(GtkWidget *w);
78 GtkWidget *w, *w1, *w2, *w3;
84 @@ -20,6 +20,6 @@
/openbmc/linux/drivers/crypto/cavium/cpt/
H A Dcpt_hw_types.h87 u64 reserved_172_19:20;
95 u64 reserved_172_191:20;
243 * aura:12; [59:48](R/W) Guest-aura for returning this queue's
248 * size:13 [44:32](R/W) Command-buffer size, in number of 64-bit words per
252 * cont_err:1 [10:10](R/W) Continue on error.
261 * inst_free:1 [9:9](R/W) Instruction FPA free. When set, when CPT reaches the
263 * inst_be:1 [8:8](R/W) Instruction big-endian control. When set, instructions,
266 * iqb_ldwb:1 [7:7](R/W) Instruction load don't write back.
277 * grp:3; [3:1](R/W) Engine group.
278 * pri:1; [0:0](R/W) Queue priority.
[all …]
/openbmc/linux/drivers/crypto/marvell/octeontx/
H A Dotx_cpt_hw_types.h96 #define OTX_CPT_PF_QX_CTL(b) (0x8000000ll | (u64)(b) << 20)
97 #define OTX_CPT_PF_QX_GMCTL(b) (0x8000020ll | (u64)(b) << 20)
98 #define OTX_CPT_PF_QX_CTL2(b) (0x8000100ll | (u64)(b) << 20)
99 #define OTX_CPT_PF_VFX_MBOXX(b, c) (0x8001000ll | (u64)(b) << 20 | \
103 #define OTX_CPT_VQX_CTL(b) (0x100ll | (u64)(b) << 20)
104 #define OTX_CPT_VQX_SADDR(b) (0x200ll | (u64)(b) << 20)
105 #define OTX_CPT_VQX_DONE_WAIT(b) (0x400ll | (u64)(b) << 20)
106 #define OTX_CPT_VQX_INPROG(b) (0x410ll | (u64)(b) << 20)
107 #define OTX_CPT_VQX_DONE(b) (0x420ll | (u64)(b) << 20)
108 #define OTX_CPT_VQX_DONE_ACK(b) (0x440ll | (u64)(b) << 20)
[all …]
/openbmc/linux/drivers/media/platform/samsung/s5p-mfc/
H A Dregs-mfc-v7.h45 #define MFC_OTHER_DEC_CTX_BUF_SIZE_V7 (20 * SZ_1K) /* 20KB */
50 #define S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7(w, h) \ argument
51 (SZ_1M + ((w) * 144) + (8192 * (h)) + 49216)
53 #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V7(w, h) \ argument
54 (((w) * 48) + 8192 + ((((w) + 1) / 2) * 128) + 144 + \
55 ((((((w) * 16) * ((h) * 16)) * 3) / 2) * 4))
H A Dregs-mfc-v8.h94 #define MFC_OTHER_DEC_CTX_BUF_SIZE_V8 (20 * SZ_1K) /* 20KB */
99 #define S5P_FIMV_TMV_BUFFER_SIZE_V8(w, h) (((w) + 1) * ((h) + 1) * 8) argument
101 #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(w, h) (((w) * 704) + 2176) argument
102 #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(w, h) \ argument
103 (((w) * 576 + (h) * 128) + 4128)
105 #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(w, h) \ argument
106 (((w) * 592) + 2336)
107 #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(w, h) \ argument
108 (((w) * 576) + 10512 + \
109 ((((((w) * 16) * ((h) * 16)) * 3) / 2) * 4))
H A Dregs-mfc-v6.h352 #define S5P_FIMV_CODEC_H264_ENC_V6 20
377 #define S5P_FIMV_TMV_BUFFER_SIZE_V6(w, h) (((w) + 1) * ((h) + 3) * 8) argument
381 #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(w, h) (((w) * 192) + 64) argument
382 #define S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(w, h) \ argument
383 ((w) * 144 + 8192 * (h) + 49216 + 1048576)
384 #define S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(w, h) \ argument
385 (2096 * ((w) + (h) + 1))
386 #define S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(w, h) \ argument
387 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(w, h)
388 #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(w, h) \ argument
[all …]
/openbmc/linux/Documentation/leds/
H A Dleds-lp5562.rst26 Value: RGB or W
46 Engine mux has two different mode, RGB and W.
47 RGB is used for loading RGB program data, W is used for W program data.
61 echo "W" > /sys/bus/i2c/devices/xxxx/engine_mux
87 .led_current = 20,
93 .led_current = 20,
99 .led_current = 20,
103 .name = "W",
105 .led_current = 20,
/openbmc/linux/tools/testing/selftests/net/mptcp/
H A Ddiag.sh98 local timeout=20
241 ./mptcp_connect -p 10000 -l -t ${timeout_poll} -w 20 \
250 ./mptcp_connect -p 10000 -r 0 -t ${timeout_poll} -w 20 \
266 ./mptcp_connect -p 10001 -l -s TCP -t ${timeout_poll} -w 20 \
272 ./mptcp_connect -p 10001 -r 0 -t ${timeout_poll} -w 20 \
288 ./mptcp_connect -p $((I+10001)) -l -w 20 \
297 ./mptcp_connect -p $((I+10001)) -w 20 \
/openbmc/u-boot/arch/arm/lib/
H A Dmemcpy.S17 W(ldr) \reg, [\ptr], #4
33 W(str) \reg, [\ptr], #4
94 4: ldr8w r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
96 str8w r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f
110 W(nop)
112 ldr1w r1, r3, abort=20f
113 ldr1w r1, r4, abort=20f
114 ldr1w r1, r5, abort=20f
115 ldr1w r1, r6, abort=20f
116 ldr1w r1, r7, abort=20f
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/openbmc/linux/arch/powerpc/crypto/
H A Dmd5-asm.S62 LOAD_DATA(w0, off) /* W */ \
66 LOAD_DATA(w1, off+4) /* W */ \
68 addi w0,w0,k0l; /* 1: wk = w + k */ \
70 addis w0,w0,k0h; /* 1: wk = w + k' */ \
71 addis w1,w1,k1h; /* 2: wk = w + k */ \
73 addi w1,w1,k1l; /* 2: wk = w + k' */ \
88 addi w0,w0,k0l; /* 1: wk = w + k */ \
90 addis w0,w0,k0h; /* 1: wk = w + k' */ \
92 addi w1,w1,k1l; /* 2: wk = w + k */ \
94 addis w1,w1,k1h; /* 2: wk = w + k' */ \
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/openbmc/linux/drivers/scsi/
H A Dnsp32.h81 #define IRQ_CONTROL 0x00 /* BASE+00, W, W */
82 #define IRQ_STATUS 0x00 /* BASE+00, W, R */
112 #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
113 #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
130 #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
132 #define TIMER_SET 0x06 /* BASE+06, W, R/W */
136 #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
137 #define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */
139 #define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */
144 #define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */
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/openbmc/linux/arch/sh/lib/
H A Dcopy_page.S211 EX( mov.l r9,@(20,r4) )
249 EX( mov.w r0,@r4 )
269 EX( mov.l r1,@(20,r4) )
271 EX( mov.w r0,@(28,r4) )
277 EX( mov.l @(20,r5),r9 )
279 EX( mov.w r0,@(30,r4) )
286 EX( mov.l r9,@(20,r4) )
299 swap.w r10,r0
301 EX( mov.w r0,@(2,r4) )
314 EX( mov.w r0,@r4 )
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/openbmc/u-boot/board/gdsys/a38x/
H A Dhre.c56 /* opcodes w/o data */
60 /* opcodes w/o data, w/ sync dst */
61 /* opcodes w/ data */
63 /* opcodes w/data, w/sync dst */
120 ptr += 2 + v16 + 1 + 20; in get_tpm_nv_size()
122 ptr += 2 + v16 + 1 + 20; in get_tpm_nv_size()
138 static int find_key(struct udevice *tpm, const uint8_t auth[20], in find_key() argument
139 const uint8_t pubkey_digest[20], uint32_t *handle) in find_key() argument
146 uint8_t digest[20]; in find_key()
170 if (!memcmp(digest, pubkey_digest, 20)) { in find_key()
[all …]
/openbmc/linux/include/linux/mmc/
H A Dmmc.h59 #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
90 #define MMC_QUE_TASK_PARAMS 44 /* ac [20:16] task id R1 */
92 #define MMC_EXECUTE_READ_TASK 46 /* adtc [20:16] task id R1 */
93 #define MMC_EXECUTE_WRITE_TASK 47 /* adtc [20:16] task id R1 */
94 #define MMC_CMDQ_TASK_MGMT 48 /* ac [20:16] task id R1b */
145 #define R1_CC_ERROR (1 << 20) /* erx, c */
256 #define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */
257 #define EXT_CSD_FLUSH_CACHE 32 /* W */
258 #define EXT_CSD_CACHE_CTRL 33 /* R/W */
259 #define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
[all …]
/openbmc/linux/arch/m68k/lib/
H A Duaccess.c24 "3: "MOVES".w (%1)+,%3\n" in __generic_copy_from_user()
25 " move.w %3,(%2)+\n" in __generic_copy_from_user()
70 " move.w (%1)+,%3\n" in __generic_copy_to_user()
71 "5: "MOVES".w %3,(%2)+\n" in __generic_copy_to_user()
79 "20: lsl.l #2,%0\n" in __generic_copy_to_user()
86 " .long 2b,20b\n" in __generic_copy_to_user()
87 " .long 3b,20b\n" in __generic_copy_to_user()
116 "4: "MOVES".w %2,(%1)+\n" in __clear_user()
/openbmc/u-boot/drivers/mtd/
H A Drenesas_rpc_hf.c22 #define RPC_CMNCR 0x0000 /* R/W */
26 #define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
37 #define RPC_SSLDR 0x0004 /* R/W */
42 #define RPC_DRCR 0x000C /* R/W */
49 #define RPC_DRCMR 0x0010 /* R/W */
53 #define RPC_DREAR 0x0014 /* R/W */
57 #define RPC_DROPR 0x0018 /* R/W */
63 #define RPC_DRENR 0x001C /* R/W */
67 #define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20)
75 #define RPC_SMCR 0x0020 /* R/W */
[all …]

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