1*43ecec16SMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0-only */ 2*43ecec16SMauro Carvalho Chehab /* 3*43ecec16SMauro Carvalho Chehab * Register definition file for Samsung MFC V8.x Interface (FIMV) driver 4*43ecec16SMauro Carvalho Chehab * 5*43ecec16SMauro Carvalho Chehab * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6*43ecec16SMauro Carvalho Chehab * http://www.samsung.com/ 7*43ecec16SMauro Carvalho Chehab */ 8*43ecec16SMauro Carvalho Chehab 9*43ecec16SMauro Carvalho Chehab #ifndef _REGS_MFC_V8_H 10*43ecec16SMauro Carvalho Chehab #define _REGS_MFC_V8_H 11*43ecec16SMauro Carvalho Chehab 12*43ecec16SMauro Carvalho Chehab #include <linux/sizes.h> 13*43ecec16SMauro Carvalho Chehab #include "regs-mfc-v7.h" 14*43ecec16SMauro Carvalho Chehab 15*43ecec16SMauro Carvalho Chehab /* Additional registers for v8 */ 16*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_MVC_NUM_VIEWS_V8 0xf104 17*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8 0xf108 18*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8 0xf144 19*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8 0xf148 20*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_MV_BUFFER_SIZE_V8 0xf150 21*43ecec16SMauro Carvalho Chehab 22*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8 0xf138 23*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8 0xf13c 24*43ecec16SMauro Carvalho Chehab 25*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_FIRST_PLANE_DPB_V8 0xf160 26*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_SECOND_PLANE_DPB_V8 0xf260 27*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_MV_BUFFER_V8 0xf460 28*43ecec16SMauro Carvalho Chehab 29*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_NUM_MV_V8 0xf134 30*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8 0xf154 31*43ecec16SMauro Carvalho Chehab 32*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8 0xf560 33*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8 0xf564 34*43ecec16SMauro Carvalho Chehab 35*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_CPB_BUFFER_ADDR_V8 0xf5b0 36*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_CPB_BUFFER_SIZE_V8 0xf5b4 37*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8 0xf5bc 38*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_CPB_BUFFER_OFFSET_V8 0xf5c0 39*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_SLICE_IF_ENABLE_V8 0xf5c4 40*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_STREAM_DATA_SIZE_V8 0xf5d0 41*43ecec16SMauro Carvalho Chehab 42*43ecec16SMauro Carvalho Chehab /* Display information register */ 43*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8 0xf600 44*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8 0xf604 45*43ecec16SMauro Carvalho Chehab 46*43ecec16SMauro Carvalho Chehab /* Display status */ 47*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DISPLAY_STATUS_V8 0xf608 48*43ecec16SMauro Carvalho Chehab 49*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8 0xf60c 50*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8 0xf610 51*43ecec16SMauro Carvalho Chehab 52*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8 0xf618 53*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DISPLAY_CROP_INFO1_V8 0xf61c 54*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DISPLAY_CROP_INFO2_V8 0xf620 55*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE_V8 0xf624 56*43ecec16SMauro Carvalho Chehab 57*43ecec16SMauro Carvalho Chehab /* Decoded picture information register */ 58*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DECODED_STATUS_V8 0xf644 59*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8 0xf648 60*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8 0xf64c 61*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DECODED_THIRD_PLANE_ADDR_V8 0xf650 62*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DECODED_FRAME_TYPE_V8 0xf654 63*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_DECODED_NAL_SIZE_V8 0xf664 64*43ecec16SMauro Carvalho Chehab 65*43ecec16SMauro Carvalho Chehab /* Returned value register for specific setting */ 66*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8 0xf674 67*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8 0xf678 68*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_MVC_VIEW_ID_V8 0xf6d8 69*43ecec16SMauro Carvalho Chehab 70*43ecec16SMauro Carvalho Chehab /* SEI related information */ 71*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8 0xf6dc 72*43ecec16SMauro Carvalho Chehab 73*43ecec16SMauro Carvalho Chehab /* Encoder Registers */ 74*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_FIXED_PICTURE_QP_V8 0xf794 75*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_RC_CONFIG_V8 0xf798 76*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_RC_QP_BOUND_V8 0xf79c 77*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_RC_RPARAM_V8 0xf7a4 78*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_MB_RC_CONFIG_V8 0xf7a8 79*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_PADDING_CTRL_V8 0xf7ac 80*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_MV_HOR_RANGE_V8 0xf7b4 81*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_MV_VER_RANGE_V8 0xf7b8 82*43ecec16SMauro Carvalho Chehab 83*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_VBV_BUFFER_SIZE_V8 0xf78c 84*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_VBV_INIT_DELAY_V8 0xf790 85*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8 0xf894 86*43ecec16SMauro Carvalho Chehab 87*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_ASPECT_RATIO_V8 0xfb4c 88*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_EXTENDED_SAR_V8 0xfb50 89*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_H264_OPTIONS_V8 0xfb54 90*43ecec16SMauro Carvalho Chehab 91*43ecec16SMauro Carvalho Chehab /* MFCv8 Context buffer sizes */ 92*43ecec16SMauro Carvalho Chehab #define MFC_CTX_BUF_SIZE_V8 (36 * SZ_1K) /* 36KB */ 93*43ecec16SMauro Carvalho Chehab #define MFC_H264_DEC_CTX_BUF_SIZE_V8 (2 * SZ_1M) /* 2MB */ 94*43ecec16SMauro Carvalho Chehab #define MFC_OTHER_DEC_CTX_BUF_SIZE_V8 (20 * SZ_1K) /* 20KB */ 95*43ecec16SMauro Carvalho Chehab #define MFC_H264_ENC_CTX_BUF_SIZE_V8 (100 * SZ_1K) /* 100KB */ 96*43ecec16SMauro Carvalho Chehab #define MFC_OTHER_ENC_CTX_BUF_SIZE_V8 (10 * SZ_1K) /* 10KB */ 97*43ecec16SMauro Carvalho Chehab 98*43ecec16SMauro Carvalho Chehab /* Buffer size defines */ 99*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_TMV_BUFFER_SIZE_V8(w, h) (((w) + 1) * ((h) + 1) * 8) 100*43ecec16SMauro Carvalho Chehab 101*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(w, h) (((w) * 704) + 2176) 102*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(w, h) \ 103*43ecec16SMauro Carvalho Chehab (((w) * 576 + (h) * 128) + 4128) 104*43ecec16SMauro Carvalho Chehab 105*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(w, h) \ 106*43ecec16SMauro Carvalho Chehab (((w) * 592) + 2336) 107*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(w, h) \ 108*43ecec16SMauro Carvalho Chehab (((w) * 576) + 10512 + \ 109*43ecec16SMauro Carvalho Chehab ((((((w) * 16) * ((h) * 16)) * 3) / 2) * 4)) 110*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_ME_BUFFER_SIZE_V8(imw, imh, mbw, mbh) \ 111*43ecec16SMauro Carvalho Chehab ((DIV_ROUND_UP((mbw * 16), 64) * DIV_ROUND_UP((mbh * 16), 64) * 256) \ 112*43ecec16SMauro Carvalho Chehab + (DIV_ROUND_UP((mbw) * (mbh), 32) * 16)) 113*43ecec16SMauro Carvalho Chehab 114*43ecec16SMauro Carvalho Chehab /* BUffer alignment defines */ 115*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_ALIGN_PLANE_SIZE_V8 64 116*43ecec16SMauro Carvalho Chehab 117*43ecec16SMauro Carvalho Chehab /* MFCv8 variant defines */ 118*43ecec16SMauro Carvalho Chehab #define MAX_FW_SIZE_V8 (SZ_512K) /* 512KB */ 119*43ecec16SMauro Carvalho Chehab #define MAX_CPB_SIZE_V8 (3 * SZ_1M) /* 3MB */ 120*43ecec16SMauro Carvalho Chehab #define MFC_VERSION_V8 0x80 121*43ecec16SMauro Carvalho Chehab #define MFC_NUM_PORTS_V8 1 122*43ecec16SMauro Carvalho Chehab 123*43ecec16SMauro Carvalho Chehab #endif /*_REGS_MFC_V8_H*/ 124