1*43ecec16SMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0-only */ 2*43ecec16SMauro Carvalho Chehab /* 3*43ecec16SMauro Carvalho Chehab * Register definition file for Samsung MFC V7.x Interface (FIMV) driver 4*43ecec16SMauro Carvalho Chehab * 5*43ecec16SMauro Carvalho Chehab * Copyright (c) 2013 Samsung Electronics Co., Ltd. 6*43ecec16SMauro Carvalho Chehab * http://www.samsung.com/ 7*43ecec16SMauro Carvalho Chehab */ 8*43ecec16SMauro Carvalho Chehab 9*43ecec16SMauro Carvalho Chehab #ifndef _REGS_MFC_V7_H 10*43ecec16SMauro Carvalho Chehab #define _REGS_MFC_V7_H 11*43ecec16SMauro Carvalho Chehab 12*43ecec16SMauro Carvalho Chehab #include "regs-mfc-v6.h" 13*43ecec16SMauro Carvalho Chehab 14*43ecec16SMauro Carvalho Chehab /* Additional features of v7 */ 15*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_CODEC_VP8_ENC_V7 25 16*43ecec16SMauro Carvalho Chehab 17*43ecec16SMauro Carvalho Chehab /* Additional registers for v7 */ 18*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_SOURCE_FIRST_ADDR_V7 0xf9e0 19*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_SOURCE_SECOND_ADDR_V7 0xf9e4 20*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_SOURCE_THIRD_ADDR_V7 0xf9e8 21*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7 0xf9ec 22*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7 0xf9f0 23*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_SOURCE_THIRD_STRIDE_V7 0xf9f4 24*43ecec16SMauro Carvalho Chehab 25*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7 0xfa70 26*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7 0xfa74 27*43ecec16SMauro Carvalho Chehab 28*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_VP8_OPTIONS_V7 0xfdb0 29*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_VP8_FILTER_OPTIONS_V7 0xfdb4 30*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_VP8_GOLDEN_FRAME_OPTION_V7 0xfdb8 31*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_VP8_NUM_T_LAYER_V7 0xfdc4 32*43ecec16SMauro Carvalho Chehab 33*43ecec16SMauro Carvalho Chehab /* MFCv7 variant defines */ 34*43ecec16SMauro Carvalho Chehab #define MAX_FW_SIZE_V7 (SZ_512K) /* 512KB */ 35*43ecec16SMauro Carvalho Chehab #define MAX_CPB_SIZE_V7 (3 * SZ_1M) /* 3MB */ 36*43ecec16SMauro Carvalho Chehab #define MFC_VERSION_V7 0x72 37*43ecec16SMauro Carvalho Chehab #define MFC_NUM_PORTS_V7 1 38*43ecec16SMauro Carvalho Chehab 39*43ecec16SMauro Carvalho Chehab #define MFC_LUMA_PAD_BYTES_V7 256 40*43ecec16SMauro Carvalho Chehab #define MFC_CHROMA_PAD_BYTES_V7 128 41*43ecec16SMauro Carvalho Chehab 42*43ecec16SMauro Carvalho Chehab /* MFCv7 Context buffer sizes */ 43*43ecec16SMauro Carvalho Chehab #define MFC_CTX_BUF_SIZE_V7 (30 * SZ_1K) /* 30KB */ 44*43ecec16SMauro Carvalho Chehab #define MFC_H264_DEC_CTX_BUF_SIZE_V7 (2 * SZ_1M) /* 2MB */ 45*43ecec16SMauro Carvalho Chehab #define MFC_OTHER_DEC_CTX_BUF_SIZE_V7 (20 * SZ_1K) /* 20KB */ 46*43ecec16SMauro Carvalho Chehab #define MFC_H264_ENC_CTX_BUF_SIZE_V7 (100 * SZ_1K) /* 100KB */ 47*43ecec16SMauro Carvalho Chehab #define MFC_OTHER_ENC_CTX_BUF_SIZE_V7 (10 * SZ_1K) /* 10KB */ 48*43ecec16SMauro Carvalho Chehab 49*43ecec16SMauro Carvalho Chehab /* Buffer size defines */ 50*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7(w, h) \ 51*43ecec16SMauro Carvalho Chehab (SZ_1M + ((w) * 144) + (8192 * (h)) + 49216) 52*43ecec16SMauro Carvalho Chehab 53*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V7(w, h) \ 54*43ecec16SMauro Carvalho Chehab (((w) * 48) + 8192 + ((((w) + 1) / 2) * 128) + 144 + \ 55*43ecec16SMauro Carvalho Chehab ((((((w) * 16) * ((h) * 16)) * 3) / 2) * 4)) 56*43ecec16SMauro Carvalho Chehab 57*43ecec16SMauro Carvalho Chehab #endif /*_REGS_MFC_V7_H*/ 58